Research And Hardware Design Of HEVC-based Deblocking Filters

In recent years,the demand for high-definition video and ultra-high definition video for multimedia entertainment is growing rapidly,which puts forward higher requirements for video coding technology.As High Efficiency Video Coding(HEVC)needs to go through the process of prediction,transformation and quantization,video compression will produce block effect,ringing effect and so on.In order to improve the image quality,loop filters(deblocking filter and sample adaptive compensation filter)are usually used in previous studies to reduce the distortion effect.However,in HEVC-based algorithms,loop filter occupies a lot of computing time,so the hardware design and optimization of loop filter algorithm has become a research hotspot.Aiming at the blocking effect and ringing effect in video coding,this paper proposes a de-blocking filter based on the improved boundary decision and boundary strength combination algorithm,and carries out the hardware design and implementation of the loop filter on FPGA.The main research contents of this paper are as follows:Firstly,the boundary determination algorithm of the block filtering algorithm is improved.Deblock filtering smoothes the pixels near the image block boundary to reduce the discontinuity of the block boundary.Aiming at the problem that the standard filtering boundary judgment algorithm is usually judged by recursion,which is not good for hardware implementation,an improved boundary judgment algorithm is proposed in this paper.The algorithm marks the boundary to be filtered according to the corresponding parameter information of Coding Tree Unit(CTU),and marks only one pixel on the block edge.The improved algorithm is easy to implement in hardware,saves storage space and reduces boundary marking time.Secondly,the boundary strength calculation algorithm is improved.Aiming at the problem of storage waste caused by the standard HEVC algorithm when calculating the boundary strength,the boundary strength merging algorithm proposed in this paper divides the boundary strength of large and small CTU into 64 boundary strengths.The subsequent filtering module does not need to transmit the boundary position mark,but directly transmits the boundary strength value of the entire CTU,which reduces the storage space requirement.Then,on the basis of the above,this paper designs the hardware architecture of the deblocking filter and the sample adaptive compensation filter based on the improved boundary decision algorithm and boundary strength merging algorithm,which are implemented in FPGA using hardware language.The filtering algorithm studied in this paper can be applied to the existing decoder structure.And make full use of FPGA platform flexible and programmable characteristics.Finally,a verification platform is built for the loop filter architecture that includes the de-blocking filter and the sample adaptive compensation filter,and the simulation verification of the designed loop filter is carried out.The standard coding software is used for comparative analysis,and the functional correctness of the designed loop filter algorithm hardware design is verified.