Research On Linearization Technology Of Short-Wave Transmitter

As the only ultra long range communication method that is not restricted by active relay,short-wave communication is considered as the last communication defense line,and despite its traditional features,it is enduring.Short-wave power amplifier is the core device of transmitter system,for which nonlinear problems,both fundamental and harmonic distortion,are always an obstacle.As the current mainstream linearization technology,digital pre-distortion can effectively improve the fundamental distortion,but it can do nothing to the latter one.Because the working frequency range of the short-wave power amplifier exceeds 4 octaves,the traditional harmonic elimination scheme is to use large and lossy filter banks,but this will restrict short-wave transmitter miniaturization and reduce the efficiency of the whole system.In view of the above issues,the use of digital harmonic cancellation technology to eliminate harmonics would be a more potential and promising solution strategy.This thesis explores the digital harmonic cancellation from such aspects as architecture,key technologies,signal delay calibration,and FPGA hardware implementation.The main research contents and innovations of this thesis are summarized as follows:1.A dynamic digital harmonic cancellation scheme was proposed based on the shortwave frequency band.The short-wave is divided into seven bands,and the state of three digital harmonic suppressors and two low-pass filters are dynamically adjusted according to the operating frequency of the power amplifier,flexibly responding to different harmonic interference.This scheme does not need to change the existing structure of the transmitter,and can capture harmonic signals at a low sampling rate.The digital harmonic suppressor can process up to 4 harmonics,even at some operating frequencies without having to turn on the harmonic suppressor,greatly reducing system complexity and hardware resource consumption.2.A harmonic parity memory polynomial RF model was proposed based on the memory polynomial RF model.With the same memory depth and nonlinear order,this harmonic model reduces the number of parameters by more than 40% compared to conventional RF models and RF harmonic models with envelope terms,while also taking into account the performance of modeling and harmonic cancellation.The test results show that using this model can reduce harmonics to-60 dBc,and improve harmonic distortion by up to 40 dB.3.A fractional delay alignment method came up based on the variance of target window.Low sampling rates leads to a decrease in the resolution of sampled samples,and brings fractional delays,which can degrade the accuracy of model identification and affect harmonic cancellation.As a commonly used method for compensating fractional delay,interpolation-based fractional alignment requires several times of interpolation,but this poses a significant challenge in terms of hardware computing and resource consumption.Combined with narrowband pulse sampling,the fractional alignment method based on target window variance reduces the computational complexity of fractional alignment and model recognition by 95% compared to fully sampled signals,and the performance of harmonic cancellation is quite similar to that of fully sampled signals.4.A test platform was built based on RFSoC,and a digital harmonic suppressor was implemented in FPGA.The RFSoC open-loop test scheme was used for rapid verification to reduce the second and third harmonics to-54.14 dBc and-55.44 dBc,respectively.