Design And Implementation Of CS Algorithm Compensation Factor Real-time Calculation Module On FPGA

Synthetic Aperture Radar(SAR)is widely used in military,economic,environmental and other fields due to its two-dimensional high resolution,all-sky and all-weather features.With the deepening of the research on the real-time radar imaging processing system,the real-time performance of the imaging processing system is one of the most critical performance indicators when it is applied in some special scenarios.Under the scenarios of missile-borne SAR back-end guidance and UAV disaster detection,the realtime performance of the radar imaging processing system has more stringent requirements.With the further development of FPGA devices,its parallel processing,rich internal resources and other characteristics,just meet the requirements of large amount of data processing radar imaging,high processing rate,is one of the high-quality options to achieve real-time radar imaging processing system.Under this background,it is of great significance to develop SAR real-time imaging processing system based on FPGA.Firstly,the principle of Chirp Scaling(CS)algorithm is described in detail,and the effect of phase compensation factor calculation on imaging quality is demonstrated,which highlights the importance of compensation factor calculation.Then MATLAB is used to carry out point-target simulation experiment of CS imaging algorithm,which lays a foundation for the subsequent transplantation of CS algorithm to FPGA platform.Secondly,in view of the specific processing steps of CS algorithm,it is mapped to FPGA platform,and a set of real-time imaging processing system based on CS algorithm is proposed,and the working mode of the system is described in detail.In the system,except the clock of DDR is 200 MHz,the clock of other processing modules is 300 MHz.By analyzing the processing efficiency of FFT module in single channel,it is established that the system will adopt four parallel processing architecture to improve the speed.Furthermore,the access efficiency of DDR is analyzed.After improving the traditional read and write access mode,a high efficiency read and write access scheme is proposed.Finally,in order to improve the real-time performance of the compensation factor calculation module and meet the requirements of system data sequence and data rate matching,the compensation factor module is designed with time-sharing reuse and pipeline,so that the total time of calculating three phase factors is about 5us while saving resources.The mapping relationship between compensation factor matrix and data stream is further demonstrated.Finally,simulation experiments were carried out using MODELSIM to verify that the calculation results of the compensation factor module have a high precision,and the system can complete the imaging processing of 512 × 512×32bits data within 701 us,with good real-time performance.According to the processing process,the worst-case estimation is performed.Theoretically,it is proved that the system can complete the imaging processing of 8192×8192×32bits data within 200 ms,and also has high real-time performance.