10-bit Low Power Column Parallel Two-Step SS ADC Circuit Design

In recent years,the imaging technology of CMOS image sensor has been developed rapidly and has been widely used in various imaging fields.CMOS image sensors with low energy consumption,low cost and high quality have been the focus of research at home and abroad.In order to improve the imaging quality of electronic products,reduce the cost and reduce the volume,it is of great significance to continuously improve and improve the low-power design of CMOS image sensors.In terms of the power consumption of CMOS image sensors,the power consumption of ADC module accounts for more than 50%of the sensor power consumption.The column parallel SS ADC has the advantages of simple structure,small area,low power consumption,slope can be shared by multiple columns,etc.,so it is the most commonly used structure of CMOS image sensors.Based on this,the paper designed a 10-bit low power column parallel two-step SS ADC.Firstly,this paper designed a low-power comparator.Without reducing the comparator clock frequency,based on the comparator operating theory,the traditional pre-amplification+dynamic latch structure is used to reduce the pre-amplification bandwidth to reduce the power consumption.In order to reduce the precision error caused by the bandwidth limitation,the error count of the counter is compensated by extending the slope range.On the premise of not changing the quantization range of ADC,the two-step structure is used for compensation,which reduces the power consumption and improves the conversion speed.For the two-step ADC structure error,a calibration method based on redundant bits is adopted in this paper.Finally,a high-quantized 5-bit resistance partial voltage ramp generator and low-quantized 6-bit current rudder ramp generator are designed to provide the ramp generation module of the comparator.The comparator is shared for two comparisons to further save area and reduce power consumption.The 10-bit low power column parallel two-step SS ADC circuit is designed using UMC110nm CMOS technology.The schematic diagram and layout design are completed.Under the premise of clock frequency of 20MHz and power supply voltage of 3.3V/1.2V,the static characteristic DNL obtained by pre-simulation is 0.2LSB/-0.3LSB.INL was 0.5LSB/-0.2LSB;At the sampling frequency of 208kS/s and the input sinusoidal frequency of 20.52kHz,the dynamic characteristics of ENOB are 9.79bit,SFDR is 78.7dB,THD is-66.6dB,SNR is 63.0dB,SNDR is 60.8dB,the average power consumption of the comparator is about 102.9μW,which is about 40%lower than the comparator with the pre-amplification bandwidth.After simulation,static characteristics DNL is 0.3LSB/-0.5LSB,INL is 0.6LSB/-0.3LSB,dynamic characteristics ENOB is 9.36bit,SFDR is 76.0dB,THD is-64.4dB,SNR is 59.5dB,SNDR is 58.2dB.the average power consumption of a single circuit is about 153.2μW,and the single column layout area is 469.115μm × 19.68μm.