Research On Gate-Level Netlist Components Identification Based On Deep Graph Attention Networks

Integrated Circuit(IC)are one of the central forces in the development of modern society.The production of IC involves multiple entities worldwide,and thirdparty suppliers may steal the intellectual property of the IC or plant hardware Trojans in the IC,causing financial losses to IC design companies and potential risks to users.Identification of gate-level netlists provides insight into circuit structure and function,and is a critical step in many types of methods such as hardware security and form al verification.Traditional gate-level netlist identification methods are time-consuming and cannot identify variants in the library,while traditional machine learning-based identification methods have the limitations of circuit information loss due to netlist conversion and cannot identify interconnected netlists.To address the above problems,this thesis proposes a graph neural network-based method for gate-level netlist component recognition,with the following main research elements:(1)Design of feature extraction method Vec2 gate.To address the problem of circuit information loss during the conversion of existing netlist to graph,this thesis proposes the feature extraction method Vec2 gate.vec2gate extracts features for each node in the graph from five aspects: port information,structure information,in-degree gates information,out-degree gates information and self-gate information.These features can fully retain the structural and functional information of the circuit and provide high-quality gate-level netlist data for the graph neural network model to enhance the recognition effect.(2)Construction of a deep graph attention network model.First,through detailed analysis of the gate-level netlist data,this thesis proposes to use the idea of decoupling the depth and range of graph neural networks in Sha Dow＿GNN to construct a deep graph neural network model.Then,in purpose of enhancing the expressiveness of deep graph neural networks,this thesis conducts an exhaustive experimental analysis,determines the specific structure and propagation layer architecture of graph neural networks,and finally constructs a deep graph attention networks model.Finally,for the problems of overfitting and shallow information being covered in the deep graph attention network model,this thesis present a combination of JK-Net and Drop Edge algorithms on GNNs to solve the problems.(3)Experimental comparison and analysis of Vec2 gate and deep graph attention network models.A more comprehensive comparison experiment and analysis is designed for the proposed feature extraction method Vec2 gate and deep graph attention networks model to validate that the proposed method surpasses the existing methods in several metrics.Experimental results on five different sized gate-level netlist datasets show that Vec2 gate achieves an average improvement of 2.57% and4.95% in Micro-F1 and Macro-F1 metrics over existing feature extraction methods,and the method in this thesis achieves an average improvement of 6.47% and 13.29%in Micro-F1 and Macro-F1 metrics over existing netlist identification methods,the average Micro-F1 and Macro-F1 of this thesis reached 99.59% and 98.86%,respectively,on the five datasets.