Research On Verification Technology Of Convolution Neural Networks Accelerator Based On UVM

Convolutional Neural Network(CNN)is widely used in various fields due to its powerful feature extraction and classification capabilities,and has enormous research value in scientific research.In recent years,the hardware acceleration of CNN has gradually become a research hotspot.In the field of artificial intelligence,due to the increasing demand for processing large amounts of data,some specific application scenario accelerators have gradually become the mainstream solution for current terminal products.The main reason is that dedicated chips can provide parallelism and customized running processes to achieve optimal performance.In addition,with the significant increase in chip design scale and the increasing requirements of semiconductor manufacturing process nodes,the functions of chips are becoming increasingly complex,making it more prone for chip designers to make mistakes.The accuracy,comprehensiveness,and stability of overall chip verification are areas that need to be emphasized during the chip development phase.First of all,the paper analyzes the platform structure,core mechanism and other aspects of the universal verification methodology by combining the hardware verification language System Verilog and the universal verification methodology(UVM).The role of various convolutional layers within CNN and the configuration of convolutional layer parameters for commonly used algorithm models were described.In addition,the main structure of the acceleration hardware used in the CNN accelerator in this article was introduced,and a detailed description of the internal design of the module was provided for subsequent verification content.Secondly,before the validation work begins,the specific functions of the module are explained,which facilitates subsequent validation work.According to the design documents,a framework diagram of the module was designed,and the relationship between interfaces was sorted out.Based on this,a verification platform was designed to facilitate the writing of code in subsequent components.In addition,because the mathematical arithmetic involved in the CNN accelerator is in the floating point format,the algorithm dedicated to floating point operation is designed using C language and modeled.The model can accurately complete the multiplication and addition of floating point numbers,which also makes preparations for the establishment of the verification platform for the pulse array module in the CNN accelerator and simplifies its verification work.In the verification work of this article,based on the concept of UVM and design specifications,a verification platform was built and the internal components of the platform were designed and filled,and communication between the components was also achieved.The work focuses on building a complete verification platform,developing various different test cases,designing the required sending incentives,and implementing the function of automatic comparison of reference models and results.Through a large number of simulations of the designed test cases,not only the coverage rate reaches the optimal coverage,but also the reusability of the verification platform is realized,and the verification work is finally completed,achieving the verification purpose required by the designers.The involved modules are designed reasonably and verified correctly,can complete the test of all function points,code coverage meets the design requirements under conditions,and all test case results are correct.In the verification work of this article,based on the concept of UVM and design specifications,a verification platform is built and the components inside the platform are designed and filled.Communication between components is also implemented.The work focuses on building a complete verification platform,developing a variety of different test cases,designing the required sending incentives,reference models,and automatic comparison of results.Through a large number of simulations of the designed test cases,not only the optimal coverage is achieved,but also the reusability of the verification platform is achieved.Finally,the verification work is completed,achieving the verification purpose required by the designer.The module involved is reasonably designed and verified correctly,and can complete the testing of all function points.The code coverage meets the design requirements when conditions permit.All test case results are compared correctly.Finally,based on the simulation results of the designed test cases,a validation result analysis was conducted on the validation work carried out,and the results of the modules validated in the CNN accelerator were analyzed in detail.After reviewing the waveform and analyzing the coverage rate,it can be determined that the validation work of the internal modules of the CNN accelerator has been comprehensively and accurately completed.