Research On 3D Heterogeneous Integrated Device Model And PDK Technology Based On GaAs PHEMT And FO-WLP Process

With the development of integrated circuits,Moore’s Law has gradually come to an end.In order to meet the requirements of miniaturization,high density,diverse functions,high performance,and low cost in electronic systems,3D Heterogeneous Integration(3D HI)technology has become a key technology for the next generation of integrated circuits.3D HI technology can integrate compound semiconductor high RF performance devices,silicon based low-cost and high integration complexity circuits,etc.into a complete 3D HI circuit,fully leveraging the advantages of semiconductor materials and device structures.Accurate 3D HI process design kits(PDK)and model can significantly reduce research and development costs and cycles,and improve circuit yield.Due to the wide variety of 3D HI technologies and the lack of a standardized system,there is currently no standard 3D HI PDK and model development solution.In order to achieve simulation design of Fan Out Wafer Level Packaging(FO-WLP)for GaAs pHEMT process chips and provide technical support for system level design,this dissertation develops a 3D HI PDK and model based on 3D heterogeneous integrated GaAs pHEMT and FO-WLP process technology.The main content is as follows:(1)Firstly,the Wafer Level Packaging(WLP)technology was introduced,and the process flow of FO-WLP was analyzed in detail.Then,the basic working principle,device structure,and process flow of GaAs pHEMT devices were elaborated.Provide a theoretical basis for subsequent 3D HI device model and PDK development.(2)Aiming at the development difficulties of 3D HI PDK,a development method for 3D HI PDK is proposed in the ADS development environment.Starting from the3 D HI PDK structure,in-depth analysis is conducted on the development of technology file,Pcell,and physical verification file,including the development of GaAs pHEMT and FO-WLP composite process substrate files,extensional mode of GaAs pHEMT process devices,and physical verification functions spanning different processes.(3)The 3D HI active and passive devices are modeled and analyzed.Based on the physical structure of 3D HI pHEMT devices,the 3D HI pHEMT small signal modeling is developed and the parameters are extracted.On this basis,the large signal model of3 D HI pHEMT devices is studied in combination with the surface potential ASM model.Then,based on the EM simulation data of 3D HI passive devices,the 3D HI passive device model was studied,mainly including resistance,capacitance,and inductance.Finally,the development of the 3D HI PDK model library was completed,and the connection between the device model and PDK was established.(4)The validation analysis is mainly conducted from the perspectives of Pcell,model,device design,circuit design,etc.of 3D HI PDK,and the validated 3D HI packaging circuit is introduced as an IP circuit into 3D HI PDK,providing technical support for subsequent system level design.The accuracy and reliability of 3D HI PDK have been ensured through verification,ensuring that 3D HI PDK can provide technical support for 3D HI circuit design.