Research On Silicon Based CMOS Heterogeneous Integrated InP HBT PDK

With the rapid progress of semiconductor technology,although CMOS devices have advanced process nodes,the feature size has gradually approached the physical limit.In addition,In P HBT devices have excellent high-frequency performance but are constrained by their own physical characteristics.Heterogeneous integration technology provides the possibility to break through device characteristics,enabling systems to have advantages such as high integration and low power consumption,which makes them have broad development prospects in the field of integrated circuits.The Process Design Kit(PDK)is a bridge between the circuit design process and the electronic design automation(EDA)tool,and it is also a key step to determine the success of streaming.The research on heterogeneous integrated PDK has profound significance,confirming the feasibility of heterogeneous integration technology,reducing the losses caused by repeated design,and effectively improving design efficiency.The specific work of this thesis is as follows:(1)In response to the physical characteristics constraints of the device itself and the lack of heterogeneous integrated PDK,this thesis conducts research on the development of heterogeneous integrated PDK for silicon based CMOS and In P HBT.The heterogeneous integration method of small chip integration provides theoretical support for the development of heterogeneous integrated PDK.Based on the PDK development platform Virtuoso tool,a complete heterogeneous integrated PDK was obtained by integrating various component structures of In P HBT PDK on the basis of the CMOS PDK library.The heterogeneous integration process technology files are sourced from the merged CMOS and In P HBT process technology files,achieving process integration.Update the PDK library architecture by redefining the library name and replacing the bound process technology files.Draw a device symbol view to represent the device.The Component Description Format(CDF)parameters,callback function,and layout pcell are all implemented by importing skill language code files,ultimately completing the development of a single device.(2)To address the issue of conflicting rules in Design Rule Check(DRC)files for heterogeneous integration,the relevant rules are processed by modifying the hierarchy definition and performing operations with unique hierarchies.By using custom type recognition devices to write Layout Versus Schematic(LVS)rule files for heterogeneous integrated layouts,device attribute design becomes more flexible.Use the include function to integrate the CMOS.drc and In P.drc rules,and use the include function to integrate the CMOS.lvs and In P.lvs rules,achieving the development of physical verification rules and providing a practical basis for subsequent DRC and LVS verification.(3)Starting from the geometric size information of CDF parameters in PDK,establish a corresponding size scaling model.Integrate the HBT HICUM model into PDK using automatic loading of model files,design the circuit in the schematic,and simulate the model using an emulator to verify the usability of the HICUM size scaling model.(4)Conduct quality assurance(QA)on the developed silicon based CMOS heterogeneous integrated In P HBT PDK library to ensure the quality of PDK.Manual QA is achieved by creating a test library,programmatic QA is achieved through QA tools,and layout automation QA is achieved through writing skill code.Establish a test pattern to verify the accuracy of DRC rules,perform DRC verification on all device layouts,and perform LVS verification on all device layout schematics.The verification results indicate that the developed silicon based CMOS heterogeneous integrated In P HBT PDK has accuracy,integrity,and reliability,and the development method is feasible.It provides a development idea for the implementation of heterogeneous integrated PDK in different processes,and has certain scientific significance.