Research And Design Of 6.25Gb/s Adaptive Decision Feedback Equalize

With the rapid development of technologies such as 5G,Io T and cloud computing,the demand for information is growing exponentially.The data processing capability of communication systems is facing a great challenge.Serial communication as the main communication method has gradually replaced traditional parallel communication.Ser Des technology is a key segment of serial communications.It is generally used in high-speed serial links.The adaptive decision feedback equalizer is an important module for Ser Des receiver.It is used to handle the inter-symbol interference in the signal.Therefore,the research and design of adaptive decision feedback equalizer has very significant application value.The main work and innovation points of this thesis are as follows.1.The basic theory associated with the decision feedback equaliser is investigated.By comparing the structures of different decision feedback equalisers,a 2-tap half-rate structure is used in this thesis.A system-level model of the adaptive decision feedback equalizer is developed using SIMULINK.The model mainly includes the channel,the least mean square algorithm,and the decision feedback equalizer.The results show that the model can correctly equalise a 6.25Gb/s signal.2.A 6.25Gb/s adaptive decision feedback equalizer is designed in 0.18μm CMOS technology.The adaptive decision feedback equalizer consists of two parts: the main circuit and the adaptive circuit.The main circuit is designed with a half-rate structure.The sub-circuit such as the add-multiplier,D flip-flop,binary data selector and output buffer are designed using a current-mode logic structure.To further extend the bandwidth,the key module add-multiplier is innovatively optimised using a negative capacitance circuit structure.The results demonstrate that the improved add-multiplier expands the bandwidth by a factor of 1.6 and reduces the delay time by 8.3ps.3.In order to ensure the stability of the tap coefficient update,the adaptive circuit is based on the continuous-time LMS algorithm and is designed using an analogue circuit approach.The adaptive circuit consists of a slicer,a subtractor,a multiplier and an integrator.Addresses the disadvantages of poor stability and high area usage in digital adaptive circuits.The presimulation results show that the "eye width" reaches 0.9UI and the "eye height" reaches 1.1V.4.The layout design and post-simulation of the circuit are completed,and the core area of the adaptive decision feedback equalizer is 300μm×240μm.The results show that the designed adaptive decision feedback equalizer can correctly equalize 6.25Gb/s data.Moreover,the "eye width" of the output eye diagram is greater than 0.82 UI and the "eye height" is greater than850 m V at all process angles,meeting the design requirements.