Research And Implementation Of Multi-channel Synchronization And Correction Technology In Wireless Channel Emulato

Wireless channel simulator is an instrument which simulates the fading characteristics of real wireless channel in communication field.With the continuous application of 5G large-scale MIMO technology,the number of channels and bandwidth of 5G channel emulators are greatly increased.Aiming at the problems existing in the hardware design of multi-channel wireless channel emulators,multi-channel synchronization and correction were designed and realized on FPGA.The main work content was divided into the following three aspects:（1）Design and implementation of multi-channel synchronous transmission.In order to solve the problem of asynchronous ADC data in wireless channel emulator,a novel ADC synchronization scheme based on JESD204B transmission interface was proposed.Compared with traditional data transmission interface,this interface has higher line rate and smaller pin number,which greatly reduces the difficulty of hardware PCB design.The synchronization scheme uses subclass 1 to align SYSREF signals for deterministic delay,thus enabling multiple ADC synchronization.（2）Research and simulation of multi-channel correction technology.Aiming at the amplitude-phase errors between multiple channels on the hardware after synchronization,a correction technology simulation based on time-domain adaptive RLS filter was proposed by comparing the existing correction algorithms.The simulation results showed that the performance of RLS correction technology was optimal,and the residual amplitude mismatch was closest to 0 d B and the residual phase mismatch was closest to 0°.（3）The realization of multi-channel correction technology.Double precision floating-point number with wider dynamic range,higher precision and significantly shorter development cycle was selected for the RLS correction algorithm designed and implemented.In order to give full play to the advantages of FPGA parallelization processing,the optimized RLS algorithm was split,and the design block diagram of series and combination was given.After writing Verilog code,the RLS algorithm with optimal correction performance was implemented on xc7z100ffg900-2 platform of channel emulator baseband processing chip.The test and verification showed that the error between the engineering implementation results and the Matlab simulation results was on the order of 10^-10,and the resource occupancy rate was only4.26%,which proved that the designed correction algorithm was effective and practical.