Research On A Universal Verification Platform For Zhongke SoC And Verification Methodology Of SoC

In order to meet the need of embedded system market for cost area and power dissipation, SoC has become an absolute solution. SoC remarkably improves the complexity relative to traditional ASIC, and reduces the design cycle based on IP block reuse. As the function of SoC increases, the device becomes more complexly. The increase of scale and function of SoC bring stricter requirement on function correctness and speed power and reliability. And the function correctness is the most important. Now about 70% of design effort is now dedicated to verification, while design for verification (DFV) takes more than half of the whole verification. DFV is a very important part in the whole flow. DFV has become the most time-wasted work, and it has become the bottleneck in the flow. The .. verification would be a big obstacle in IC design, if it had not been pay more attention on. In order to deal with the problem, some verification methods are present by many verification experts. To a certain extent, some methods alleviate the pressure of verification, but there is no breakthrough on verification. So now we have to integrate these methods to make the verification smoother. With the increment of the pressure of time-to-market, DFV has become one of hot points in the chip area.The work of this paper is subproject of "Advanced 32-bits Embedded Processor and Study of SoC Platform Design" . The paper expatiates on the development of bus verification IP and universal verification platform. Firstly, we introduce the background of our work, which includes the design technology of SoC and our SoC which named Zhongke SoC in detail and the flow of SoC verification. In chapter 4, we introduce some popular and wide-used verification method, and then present a verification method integrating kinds of technology. Then in the following 2 chapters, we introduce how to design the APB verification IP(VIP) and the universal verification platform which are both based on the method in detail. APB VIP can be used to verify an APB RTL design by a designer or a verification engineer. It is very easy to set up the Testbench and generate the testcases for...