Research On Communication Twisted Pair Monitoring System Based On FPG

Communication twisted pair is commonly used in x DSL(x Digital Subscriber Line)network wiring and widely used in aircraft,railway,ships,and other scenarios.The wire is prone to aging and damage and it is difficult to troubleshoot manually in the case of long-distance and hidden wiring.The main trouble faced by the existing fault detector include:(1)Severe attenuation of signals in long distance twisted pairs;(2)The existing system schemes are difficult to ensure both accuracy of fault locating and system body lightweight design.FPGA(Field Programmable Gate Array),with parallel data processing capability,have not been used more reasonably in the system.This thesis studies the long-distance fault detecting of voice communication twisted pair with low transmission bandwidth and the application of FPGA in the twisted pair fault detector.The main work is as below:(1)The equivalent circuit model of lossy uniform transmission line is analyzed,and the RLCG(Resistance,Inductance,Capacitance and Conductance)model of voice communication twisted pair is established based on AWG(American Wire Gauge)wire specification standard.The reflection coefficient,transfer function and signal speed are calculated according to the RLCG parameter,and the frequency selecting range of excitation signal is 10 MHz or below.The signal propagation speed varies obviously with the frequency,so it must correspond to the frequency in application.(2)The research and comparation on several fault detecting methods based on traveling wave locating method TDR(Time Domain Reflectometry)/FDR(Frequency Domain Reflectometry)/SSTDR(Spread Spectrum Time Domain Reflectometry)/TFDR(Time Frequency Domain Reflectometry)indicate the advantages in the application of TFDR.A design method of excitation signal suitable for long-distance detection is proposed based on TFDR.As to the tedious time-frequency analysis and joint time-frequency cross-correlation calculating process of TFDR,propose a simplified calculating method using envelope extraction method,to reduce the implementation complexity of the whole system.(3)The logic design of the twisted pair fault monitoring system based on FPGA is as follows: the call status detection module and signal parameter configuration module for monitoring requirements are realized.The drive clock with frequency over 50 MHz is provided by FPGA,and the high-speed signal is sent and received simultaneously with the parallel port high performance AD/DA(Analog to digital /Digital to analog)device.Design envelope extraction calculation module,complete the fault detection;To improve the calculation frequency of the system,the circuit structure is optimized,and the clock domain crossing processing is introduced.And time sequence constraints are set to ensure the stability of the digital logic system.In practice,the excitation signals designed in this thesis is applied to the twisted pair fault detecting.The detecting error rate can be controlled below 2% by selecting the signal stimulus reasonably.The move can effectively deal with the long-distance twisted pair detecting requirements of long-distance and high attenuation twisted pair fault detecting,while reducing the complexity of the system implementation.The system and effectively reduce the complexity of system implementation.