Research On ESD Protection Unit Based On UTB-SOI Technology

With the continuous development of integrated circuits,when the feature size is reduced to below28 nm,Ultra-Thin-Body silicon-on-insulator(UTB-SOI)devices have significant advantages in lowpower and cost-effective application due to their unique back gate bias,small parasitic capacitance,and good planar process compatibility.However,due to the reduction of the design window,devices implemented by UTB-SOI process are more sensitive to electrostatic discharge(ESD).The use of buried oxide(BOX)increases the heating phenomenon of devices,making UTB-SOI devices more prone to failure than bulk devices when facing ESD,increasing the difficulty of protection design.In order to meet the needs of ESD protection in UTB-SOI technology,an ESD protection structure suitable for thin gate oxide devices has been designed based on a detailed analysis of traditional ESD protection devices.The main research work and achievements include:(1)A solution combining bulk SCR with SOI-ggNMOS is introduced to address the issues of slow opening and high trigger voltage in traditional SCR structures.In the proposed device structure,ggNMOS on a thin silicon layer is used as an assisted triggered element.When an ESD event occurs,the ggNMOS source injects electron into the bulk well region below the BOX layer,reducing the trigger voltage of the proposed device.By optimizing the key parameters of this device,the triggering voltage Vt1 reduced from 12.1 V to 5.8 V,the holding voltage Vh reduced from 4.6 V to 2.5 V,and the second breakdown current It2 also increased.The ESD protection performance has been greatly improved,meeting the ESD protection requirements of thick gate oxide devices.(2)A novel ESD protection structure with ggNMOS and PNP dual-assisted triggered SCR is proposed based on the SOI-ggNMOS assisted triggered SCR structure.The new structure adds an additional parasitic bulk PNP transistor current discharged path,which is parallel to the original ggNMOS current path to assist the triggering of SCR main discharged path,further reducing the device’s trigger voltage and improving the device’s ESD current discharged ability,making it suitable for ESD protection of thin gate oxide devices.The analysis of key device parameters was conducted to achieve optimal ESD protection performance of this structure,with triggering voltage Vt1=1.41 V and holding voltage Vh=1.19 V,meeting the ESD design window of 0.99-2.5 V for thin gate oxide devices.Moreover,by changing the key parameters,the trigger voltage can be adjusted over a wide range to achieve different ESD protection applications.