Research And Design Of Double Dielectrics Enhancement LDMOS

Lateral double diffusion metal oxide semiconductors（LDMOS）based on silicon on insulator（SOI）technology have a wide range of applications in power semiconductor integrated circuits due to their high breakdown voltage,high integration,strong drive capability and low power losses.Breakdown voltage（BV）and specific on-resistance(R_on,sp)are the two key performance parameters of SOI LDMOS.How to improve the breakdown voltage and reduce the specific on-resistance to achieve a good compromise between them is one of the important goals pursued by academics and engineers.High K dielectric and low K dielectric are often introduced into the design of semiconductor power devices due to their special dielectric constants.The application of both dielectric materials can enhance the breakdown characteristics and reduce the specific on-resistance of semiconductor power devices.In this thesis,a new structure of double dielectrics enhanced LDMOS based on SOI technology,high K dielectric technology and low K dielectric technology is proposed,the main work includes:（1）A new structure of double dielectrics enhanced LDMOS（DDE LDMOS）is proposed.The main feature of this structure is that the device uses a high K dielectric for the gate field dielectric and a low K dielectric for the buried layer.The high K field dielectric effectively modulates the surface electric field and potential of the device,reduces the peak electric field at the PN junction,while optimizes the doping concentration in the drift region and reduces the on-resistance of the device.The high K gate dielectric can reduce the device threshold voltage and improve the gate control capability of the device.The low K buried layer dielectric enhances the electric field strength of the buried layer and enhances the vertical breakdown voltage.By investigating the effects of the dielectric constants of high K and low K dielectrics and key structural parameters such as doping concentration in the drift region on the device performances,the optimal electrical performance of DDE LDMOS is achieved.The results show that the breakdown voltage of DDE LDMOS is increased by 61.9%,the specific on-resistance is reduced by 19%and the FOM value is increased by 222.4%compared to conventional SOI LDMOS.（2）A two-dimensional analytical model of the double dielectrics enhanced LDMOS is established.The two-dimensional Poisson’s equation is solved considering the influence of high K field dielectric and low K buried layer dielectric on the boundary conditions,and the analytical models of electric field potential distribution,breakdown voltage and optimal doping concentration in the drift region of DDE LDMOS are established.The validity of the device model is verified by fitting the analytical models to the simulation results.（3）A new structure of double dielectrics enhanced Fin LDMOS（DDE Fin LDMOS）is proposed.This structure features a high K dielectric layer deposited on the fin active region and a low K dielectric used in the buried layer.The high K gate dielectric widens the channel width while reduces the threshold voltage of the device,the high K field dielectric aids depletion from the top and sides of the drift region,optimizes the potential field distribution and doping concentration in the drift region,which significantly increasing the breakdown voltage and decreasing the specific on-resistance.the low K dielectric enhances the vertical breakdown voltage and increases the electric field strength of the buried layer.Compared with conventional SOI LDMOS with the same structural parameters,the breakdown voltage of DDE Fin LDMOS is increased by 292%,the specific on resistance decreased by 31%,and the FOM value increased by 1200%.