Research And Verification Of Chiplet Universal Test Technology For Complex Stacked Structures

In the post-Moore era,relying on the development of more advanced process nodes to improve the performance of chip products has become an unsustainable and uneconomic solution,and Chiplet technology is the most critical heterogeneous integration method of chips in the current integrated circuit industry,which can meet the market demand for high-performance and low-cost chips.Many kinds of multi-Chiplets integrated systems with complex stacked structures are derived from Chiplet technology,so it brings many new challenges to the design for test of 3D stacked integrated circuits.In order to solve the problem that it is difficult to access the test structure in each Chiplet across layers in the post-bonding test stage,this paper studies the efficient post-bonding test of multiChiplets integrated systems with different stacked structures,and a Chiplet universal test technique for complex stacked structures is proposed,and a Chiplet Universal Test Access Port Controller(CUTAPC)circuit is designed.Taking the 2.5D multi-Chiplets integrated system based on passive interposer and active interposer,the 3D multi-Chiplets integrated system based on passive interposer,and the multi-towers multi-Chiplets integrated system based on passive interposer and active interposer as the research objects.The CUTAPC circuit is selectively inserted into the Chiplet or active interposer of each multi-Chiplets integrated system as the test controller of their respective test structures,all test controllers are serially connected into a test scan chain,that allowed testing access to all components of each layer through transmitting test patterns from external test ports.The CUTAPC circuit includes the Chiplet Dedicated Finite State Machine(CDFSM)circuit,the Chiplet test configuration circuit,the Chiplet test instruction circuit,the Chiplet test data circuit and the Chiplet test interface circuit.Among them,the CDFSM circuit is a 23-bit finite state machine that outputs configuration register enable signals,instruction register enable signals,data register enable signals and test output selection signals,and supports fast access to configuration register.The Chiplet test configuration circuit outputs four configuration signals through which an effective test path of multi-Chiplets integrated system can be set accurately and efficiently.The Chiplet test instruction circuit enables the Chiplet test structure to work in various test modes.The Chiplet test data circuit is used to access the test network selected according to the test instructions and to transmit test data.The Chiplet test interface circuit satisfies the interoperability and controllability of the test ports between each Chiplet.Based on three different Chiplets,multi-Chiplets integrated systems with five kinds of stacked structures are constructed in this paper,which verifies the feasibility of the proposed "Universal Chiplet Test Technology for Complex Stacked Structures".The experimental results demonstrate that the CUTAPC circuit is suitable to design test structure of multi-Chiplets integrated system with complex stacked structures,and can be used as the standardized test controller for Chiplet.In the five stacked application scenarios,compared with the Chiplet test technique proposed by IEEE 1838 standard,the Chiplet test technique based on CUTAPC circuit takes at least 27.91% less time during the stage of configuring effective test path,and at least 29.17% less time during the stage of setting test,and at most 0.85% more area of the inserted circuit.