Research On Test Structure Optimization For 2.5D Integrated Circuit

The interposer-based 2.5D IC changes connection mode of traditional 2D IC,which adopts structures such as TSVs to realize interconnection in another dimension between the chips.Thereby,it overcomes the problems like wire delay and power consumption faced by the semiconductor industry today.2.5D ICs improve system performance,reduce power consumption,and support heterogeneous integration.However,high integration and complexity lead to inevitable defects during fabrication and lifetime.In particular,the structure of 2.5D IC is different from the traditional 2D IC structure,which brings many new challenges to the test.This paper proposes effective test schemes targeting on silicon interposer and dies of the 2.5D IC in the three stages of pre-bonding,post-bonding,and normal operation of the die respectively.The main contents are as follows:In pre-bond stage,since the silicon interposer is a key component of a multi-die package as in a 2.5D IC,testing of the interposer before die stacking is essential to minimize the yield loss that results from the stacking of good dies on a defective interposer.This paper presents the application of time domain reflectometry(TDR)to pre-bond testing of silicon interposer.The proposed test structure utilizes e-transmission gates to connect separated interconnects into one test path during testing.Thus,by applying the test stimulus pulse,the emission pulse will be reflected on the fault point because the impedance of it differs from that of transmission line.In addition,in order to improve the test accuracy,the signal is denoised by wavelet transform and analysized by support vector machines.In post-bond stage,this paper proposes a new test method targeting open,short and delay defects in functional paths.First,we modify the traditional boundary scan cell structure to lower test power consumption.Since the available test pins are limited,we propose a data-package based test data transmission structure to coordinate the quantity of test data transferred per unit time between a small number of TSVs and multiple TAMs,which makes full use of the high throughput of TSVs.In order to implement at-speed interconnect testing,this paper designs a test clock switch module,and improves the test access port controller of IEEE 1149.1.Since it is infeasible to monitor circuit delay of an endless number of long(critical)paths that are most likely to fail first over the chip lifetime,an on-chip health monitoring method based on DE-Cluster algorithm for 2.5D ICs is proposed to appropriately select a small subset of critical paths to carry out delay detection,based on which the delay information of the rest large number of circuits can be predicted accurately.The proposed method considers all phenomena that may cause timing violation of circuits.The selected representative critical paths are extracted by analysing the topological,electrical,spatial,and functional similarities among different critical paths.The validity of the proposed test structure is verified by simulation experiments.The results show that the above test design can effectively overcome various test constraints and meet the test demands of 2.5D IC at each stage.Moreover,they achieve the reduction of test power consumption,test time as well as test costs.