Research And Design Of Sub-Sampled Wideband Phase-Locked Loop

The design and optimization of phase locked loop(PLL)will continue to become a hot topic of research to meet the growing demand for communication and application scenarios.The PLL in high-speed SERDES transceivers will face more challenges and opportunities.On the one hand,the phase locked loop needs to have lower jitter to reduce the error rate of information transmission,ensure stable and accurate data transmission and reception by high-speed SERDES transceivers,and meet the requirements of continuously improving communication rates.On the other hand,as more and more communication protocols have been proposed in recent years,phase locked loops need to have a wider output frequency range and better compatibility to meet the requirements of different standards.However,the current clock source of high-speed SERDES transceivers uses a self biased phase locked loop with large output jitter,which makes it increasingly unsuitable for future research and development of high-speed SERDES transceivers.In recent years,in the literature research on sub-sampling phase-locked loops,it has been found that sub-sampling phase-locked loops can improve the jitter and spurious performance of phase-locked loops.Applying sub-sampling phase-locked loops to highspeed SERDES transceivers will further reduce clock jitter.However,at present,the loop bandwidth of subsampling phase-locked loops is a constant value.When the frequency variation range is large,the output jitter changes greatly,making it unable to be directly applied to high-speed SERDES transceivers.Therefore,in this thesis,in view of the constant gain of the charge pump in the traditional sub-sampling PLL,which limits the performance of the wide frequency range output,a sub-sampling wideband PLL with a wide output frequency range is designed.This design combines a subsampling phase locked loop and a self biasing phase locked loop,and uses an adaptive pulse width matching circuit to adaptively control the charging and discharging time of the subsampling charge pump.This allows the gain of the subsampling charge pump to be adaptively adjusted with the input reference frequency,achieving the goal of linearly changing the loop bandwidth with the input reference frequency,and maintaining a constant damping factor,thereby expanding the frequency locking range and reducing output jitter.In this thesis,Based on the small signal models of self-biased PLL and sub-sampling phase locked loop,the small signal model of sub-sampling wideband phase locked loop is derived.By analyzing the small signal model of sub-sampling wideband phase locked loop,it is theoretically demonstrated that the sub-sampling wideband phase locked loop can achieve adaptive adjustment of loop bandwidth with input reference frequency,and the damping factor is basically unchanged.At the same time,the noise model of the subsampling wideband phase locked loop is analyzed,and the noise source of the subsampling wideband phase locked loop is described.Compared with the annoying noise of the self-biased phase locked loop,it is confirmed that the sub-sampling wideband PLL can output a low jitter clock.Based on the theory of sub-sampling wideband phase-locked loop,a 40 nm CMOS process is used to build each module and system circuit of the sub-sampling wideband phase-locked loop,and the overall simulation is performed using HSPICE tools.The simulation shows that it can stably output a low jitter clock in the frequency range of3.125～6GHz,with an RMS jtter of 352 fs,a reference spurious of-48 d Bc,and a phase noise of-110.98 d Bc/ Hz@1MHz 。...