Study Of Interpolation Filter For 16bit Sigma-Delta DAC

With the recent surge in consumer electronics,audio and video codec modules have entered the digital era,signifying an increasing demand for higher precision in key components such as analog-to-digital converters(ADC)and digital-to-analog converters(DAC)within the codec modules.The Sigma-Delta DAC,incorporating oversampling and modulation techniques,has emerged as a prominent research focus both domestically and internationally due to its notable features such as high conversion accuracy and integration capability.The essence of oversampling technique lies in utilizing digital signal processing methods to significantly improve the sampling accuracy of the input signal prior to digitalto-analog conversion.The interpolation filter plays a crucial role in implementing oversampling technique.According to the characteristics of audio and video signals,a two-stage,two-times interpolation half-band(HB)filter and a one-stage 32-times interpolation CascadedIntegrated-Comb(CIC)filter were designed using Simulink modeling.By cascading three filter stages,a total oversampling factor of 128 was achieved.This paper presents the following optimizations in hardware circuit design:(1)This article employed CSD encoding to process the coefficients of the two-stage HB filter.To achieve the convolution between the filter coefficients and the input sequence,we designed a fixed-coefficient CSD-encoded multiplier IP core based on the shift and addition principle and binary trees.The simulation results demonstrate that the CSDencoded multiplier reduces resource consumption by approximately 50% compared to the shift-and-add multiplier.(2)Area-Optimized the three-stage interpolation filter using the polyphase folded structure and Nobel principle.The polyphase folding structure extends the HB filter folding architecture by multiple decomposition techniques,thereby reducing the usage of the tool of zero insertion at the front end of the interpolation system.Additionally,it achieves cyclic output of the odd and even branches through a timing control module.The Nobel principle has reduced the use of delayers in multi-level CIC filters.The temporal simulation results demonstrate that the optimized three-stage filter is still capable of filtering out the aliasing frequencies generated by the zero-insertion method,achieving a 128-fold oversampling.(3)Front-End Design and FPGA Validation of a Multistage Interpolation Filter Chip.Utilizing the Chipscope Module for observing output signals of FPGA and performing Fourier Analysis in MATLAB.The maximum signal-to-noise ratio(SNR)of the multistage interpolation system within the frequency range of 0～3.5KHz is calculated to be 106.18 d B,with an effective number of bits(ENOB)of 17.34 bits,satisfying the specified requirements.