Design Of High-speed Data Transmission Interface Based On FPGA

In recent years,with the rapid development of high-speed data acquisition system and high-speed data transmission technology,the performance requirements for highspeed data transmission interface are getting higher and higher.As an important component,the high-speed data transfer interface directly affects the overall system stability and data transfer rate.Based on this background,this dissertation designs highspeed data transmission interface based on Xilinx FPGA GTP high-speed serial transceiver,which supports high-speed serial interfaces such as SRIO interface,10 Gigabit LAN port,optical fiber interface and PCIe bus interface.The details of the study are as follows:This dissertation analyzes the high-speed data transmission interface technology and designs the hardware board based on FPGA GTP high-speed serial transceiver,mainly including the design of high-speed data transmission interface based on PCIe bus and SFP+ fiber optic interface.PCIe bus interface is used to realize the communication between FPGA board and PC,and SFP+ fiber optic interface receives external optical signal.To meet the functional requirements of the above interfaces,the PCIe bus interface circuit and SFP+ fiber optic interface circuit are designed.DDR3 cache circuit is designed for the problem of mismatch between PCIe bus interface and fiber interface transmission rate.Design power system circuit for Xilinx 7 series FPGAs to provide stable power supply for PCIe bus interface,SFP+ fiber interface circuit,and DDR3 memory circuit.Design FPGA configuration circuitry for Xilinx 7 series FPGAs,using the main BPI mode to ensure that logic code can be loaded quickly after FPGA power-up.PCB lay-out design for high-speed signal transmission technology using cadence17.4 to ensure the signal integrity of high-speed signals and power integrity of the power supply system to ensure the reliability of the system hardware.Design the high-speed data transmission interface logic based on Vivado software to connect the transmitter and receiver of two SFP+ optical port modules using fiber optic cables to achieve data loopback.Design the optical port module logic code to encode the data according to 8b/10 b and align and decode the loopback data words.Design the DDR3 data cache module to implement DDR3 memory read/write operation,store the data decoded by the optical port into DDR3 memory,and then read the data out.Design the PCIe read/write module with XDMA IP core as the core,read DDR3 memory data and send it to PC side through PCIe write module.Finally,the logic design is verified on the designed hardware board to validate the function of the hardware board.This dissertation designs the logic design and hardware board of PCIe 2.0 bus interface and SFP+ fiber interface based on FPGA GTP high speed serial transceiver.PCIe bus interface adopts 4-channel design and uses XDMA IP core to realize data read/write,and its read/write rate can reach 1369MB/s and 1597MB/s.SFP+ fiber interface has good eye diagram status at 6.25Gb/s rate.The SFP+ fiber interface has good eye diagram status at 6.25Gb/s.The correctness of DDR3 data reading and writing,PCIe bus data transfer,and SFP+ fiber interface data transfer is verified by Vivado software simulation.In addition,the logic of the hardware board designed in this dissertation is verified,and the correctness of the logic design and hardware design of this dissertation is further verified by comparing the transceiver data with the upper computer.