Design And Research Of CMOS Process In SiC Integrated Circuit

Confronted by the challenges of global climate change,China has taken the lead in proposing a "Double Carbon" policy to restructure its energy industry and reduce its reliance on traditional fossil energy sources.Therefore,it is crucial to improve the energy efficiency.With the continuous development of third-generation semiconductor technology,SiC power devices have shown their extraordinary performance advantages.Compared to Si power devices,SiC power devices have the advantages of faster switching speeds,lower on-resistance and higher power efficiency.Currently,SiC power devices are widely used in new energy applications such as photovoltaic power generation and electric vehicles.However,currently SiC is only used to fabricate power modules,while low-voltage analog and mixed-signal control circuits in the system are fabricated using traditional Si CMOS technology.This scheme significantly increases the impact of parasitic parameters in the power system and reduces the power density.To address these issues,this dissertation proposes developing a SiC CMOS process technology to integrate low-voltage control circuits with power modules to improve the overall efficiency of the power system.First of all,the SiC CMOS fabrication process flow was designed by referring to the Si CMOS process flow.The finite element semiconductor simulation tool Sentaurus TCAD has been employed to simulate the fabrication process of SiC low-voltage planar NMOS and PMOS devices.By comparing and analyzing the characteristics of the devices with various process parameters,the epitaxial layer concentration,the P-well doping concentration and depth,the gate oxide thickness,the nitrogen ion implantation dose in the NMOS channel region,and the doping type of the polycrystalline silicon gate were designed and optimized.The ion implantation process parameters was designed by using the simulation tool SRIM.Subsequently,combining SiC power device process and the process parameters simulated in Chapter 2,the SiC CMOS fabrication process flow was determined.Based on the designed process flow,the 4H-SiC CMOS devices have been fabricated in the clean room.To evaluate the critical process steps,such as ion implantation,gate oxide and ohmic contact,some test structures have been fabricated and measured.The interface state density near conduction band extracted by C-V characterization of MOS capacitors is below 7 × 1011cm-2eV-1,while the interface state density near valence band is below 1 × 1013cm-2eV-1.The n-type specific resistivity is 8.95 ×10-6Ω·cm2 and the p-type specific ohmic contact resistivity is 1.78 × 10-4Ω·cm2.The electrical characteristics of the 4H-SiC CMOS device have been characterized.The effects of gate oxide thickness,channel region implantation,and device size on the device performance have been analyzed.The channel carrier mobilities have been extracted from the static characteristics.The typical NMOS mobility is 19.4 cm2/V·s and the PMOS mobility is 5.7 cm2/V·s.The impact of different design parameters on mobility has also been analyzed.The results of this lot meet the design requirements of 4H-SiC CMOS integrated circuits,establishing the foundation for the fabrication of SiC power integrated circuits.