Design Of Low Power Instruction Cache For MCU

With the rapid development of the Internet of things,the demand for low-power microcontroller unit(MCU)is increasing.The frequent access of instruction and data in memory leads to high dynamic power consumption of MCU in operative mode.The use of instruction cache can reduce the access of memory effectively.In this way,the power of memory is reduced while the performance of MCU is improved.Therefore,reducing the power consumption of instruction cache in the Ultra-Low Power Microcontroller unit(ULPMCU)is the key to reducing the dynamic power consumption of ULPMCU.Due to redundant access power existing in traditional instruction cache,a self-timed serial access method is proposed firstly.By implementing self-timed circuit and comparison circuit,the dynamic power consumption of the missed cache can be reduced,meanwhile,the access of instruction cache can be completed in one cycle.Secondly,circuit sharing technology based on static random access memory(SRAM)is proposed.By sharing one sequential circuit and decoding circuit for every two pieces of DATA SRAM,the area of sequential circuit and decoding circuit can be saved by 11% and the write power consumption can be reduced by 33%.In addition,each SRAM adopts word line segmentation technology,which reduces the bit line precharged power consumption by three quarters by dividing the array into four blocks.Based on the low-power technologies mentioned above,a 64 KB instruction cache is designed using 22 nm process.For different load scenarios,the instruction cache proposed supports two working modes:(1)parallel access mode for high load scenarios;(2)self-timed serial access mode for low load scenarios.In addition,static power is reduced by power gating technology.Compared to the cache composed of commercial compiler SRAM,in serial access mode,the instruction cache designed in this paper reduces 29% read power when instruction hits,and 53.3% read power and 23%Energy Delay Product are reduced when instruction misses.In the parallel access mode,11% Energy Delay Product is reduced.In the shutdown mode,99.5% static power is reduced.