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Research Into Reliability Mechanisms And Models For High-voltage SOI-pLDMOS

Posted on:2016-07-19Degree:DoctorType:Dissertation
Country:ChinaCandidate:S Y LiuFull Text:PDF
GTID:1108330503976655Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The power integrated device based on SOI material owns high integration density, low static power dissipation, swift switch speed and strong anti-latchup capability. The p-type lateral double-diffused MOS (pLDMOS) as a high-side driver can simplify the power integrated circuit and reduce the chip size. Therefore, SOI-pLDMOS device has been widely used in flat panel display driver, floating gate driver, power management and audio power amplifier. For the past few years, many novel SOI-pLDMOS devices have been presented, making the switch characteristic, the current density and the breakdown voltage improve significantly. However, the reliability issues of the SOI-pLDMOS device are still serious, even restricting the further development of the device. Consequently, it is urgent to investigate the reliability mechanisms and models of the SOI-pLDMOS in detail, which has important significance for developing the SOI-pLDMOS device and the related power integrated circuit with long lifetime.In this thesis, based on the practical system application requirements, the reliability issues including hot-carrier degradation, dv/dt stressing damage and ESD failure have been investigated in detail, the inner reliability mechanisms and models have been presented. Moreover, the novel SOI-pLDMOS structures with high reliability are also reported, which have been used in the high-voltage display driver ICs. During the research process,10 SCI-indexed papers have been published,4 international meetings papers have been presented and 10 Chinese invention patents have been applied (1 Chinese invention patent has been granted). In addition, the research achievements in this thesis have obtained the Is prize of the Ministry of Education Technology Invention as the important contents (ranked at the 4th place). Main innovation points in this thesis are shown as follows.1、It has been shown that the degradation mechanisms of the SOI-pLDMOS under Ibmax stress are the interface states generation in the channel region and the hot-electrons injection into the polygate terminal region, however, the degradation mechanisms under Imax stress are the interface states generations both in the channel region and p-drift region, and there are also hot-holes injecting into the gate oxide. Based on the mechanisms, the hot-carrier degradation lifetime model of SOI-pLDMOS has been established, and the model error is less than 2%.2、A novel SOI-pLDMOS with inverted HV-nwell has been proposed. The device not only increases the off-state breakdown voltage and on-state current density by 11.3% and 10%, respectively, but also reduces the hot-carrier degradation obviously, making the lifetime of the SOI-pLDMOS increase by 25%.3、It has been shown that the failure mechanism of the SOI-pLDMOS under dv/dt stress is the trigger of the parasitic PNP transistor induced by the reverse-recovery current. The failure model of the SOI-pLDMOS under the dv/dt stress has been also presented, which error is less than 8%. Moreover, a novel SOI-pLDMOS with a high-doped n++ layer under the source p+ region has been proposed, which can restrict the trigger of the parasitic transistor and improve the anti-dv/dt capability by 34%.4、It has been found that the ESD response behavior curve of the SOI-pLDMOS does not have the snapback phenomenon, thereby, the curve can be only divided into the blocking region, the avalanche region and the second breakdown region. The current paths, impact ionization distributions and the hot-spot shifts in the above regions have been also investigated. In addition, the ESD response model of the SOI-pLDMOS has been set up, which error is less than 7%.5、A novel SOI-pLDMOS with double HV-wells has been proposed, which can increase the ESD robustness and the off-state breakdown voltage 50% and 13%, respectively. Meanwhile, the additional masks can be saved.6、Based on the proposed high reliable SOI-pLDMOS, a SOI high-voltage display driver IC has been developed and fabricated. The chip has passed all the reliability evaluations of Sumsang and Changhong corporations, and the sale quantity has exceeded one million.
Keywords/Search Tags:SOI-pLDMOS, hot-carrier, dv/dt, ESD, reliability mechanism, model
PDF Full Text Request
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