Trigger System Design And Realization Of At Of Besiii Tof Child

The primary purpose of particle physics experiment is to get the knowledge of particles, such as the variety, structure, interaction and so on. It is required to collect the vast prompt output signals from FEE (Front End Electronics) systems of various detectors for analysis. But there are many background signals brought in by miscellaneous noises, which will increase the burden of data acquisition system. We need to distinguish them from useful signals and throw them away. This purpose is fulfilled by the Trigger System. The TOF (Time of Flight) Trigger System described in this paper is one of the sub trigger systems in BESIII (Beijing Spectrometer III) which will running on BEPCII (Beijing Electron Positron Collider II). It takes in charge of the trigger judging process of TOF hit information and sends the result to GTL (Global Trigger Logic). It also assists the work of other sub trigger systems.Compared to traditional design, higher speed and density of data processing is demanded for trigger systems now because of the upgrading speed and intensity of particle colliders. So as to avoid the dead time which is caused by the delay of trigger processing, multilevel trigger method is usually adopted by traditional trigger systems. The first level trigger should be completed before the next collision happens. But for colliders nowadays, the period of collisions becomes shorter while its intensity becomes higher. The multilevel is not adaptable any longer and new method is expected to be researched. Meanwhile, there are more and more signals to be processed for the trigger system. It is requested to find efficient ways to deal with them. Highly integrated FPGA/CPLD chips can meet this requirement. Besides, the logic running within them is changeable, which greatly enhances the flexibility of trigger system.Combined with actual requirements of BESIII TOF Trigger System, further realization of the design should be considered carefully, such as the processing flow of trigger judging, technologies of high speed data transferring, application of the on-line data acquisition bus, ways to control the TOF trigger system and so on. What we are pursuing is a trigger system which is reconstructive, reliable, economical and has no dead time. The function of on-line simulation and check is also required for the convenience of system proof and diagnosis.Chapters and content of this paper are arranged as below:Chapter One of this paper introduces the background of the TOF Trigger System design first, including the foundation and develop of BEPC and BES. Meanwhile, it points out the work of this paper and primary requirements of our design.Based on the introduction of detectors and trigger systems in particle physics experiments, Chapter Two describes the physics background of BESIII TOF Trigger System and reveals the purpose of design. TOF Trigger System provides for the whole Trigger System with the precise time information, hit number, position information, back-to-back information and so on.Chapter Three will analyze the scheme of the BESIII TOF Trigger System design, including the application of the on-line data acquisition bus, the realization of reconstructive system, methods of intersystem high speed data transferring, the structure of TOF Trigger System and so on. Different from traditional ways, BESIII TOF Trigger system will buffer signals from TOF FEE System. Together with the pipeline dealing technique, there will exist no dead time. Chapter Four gives out the electronics design of BESIII TOF Trigger System in detail. The operation of TOF Trigger System is based on 9U VME bus backplane. And all the logic control and data processing in TOF Trigger System is accomplished by FPGA. The whole system consists of a 9U VME TOF Trigger module and its corresponding rear transition module. The 9U VME TOF module has the function of remote on-line FPGA configuration, which enables the real-time update of trigger logic.Chapter Five analyzes the implementation flow of trigger judging logic particularly. VHDL (Very High Speed Integrated Circuit Hardware Description Language) is employed to design the FPGA logic. Time for system design and test is much saved in this way. And so as to save logic sources and obtain higher efficiency, combination logical circuit is adopted to work together with sequential logical circuit for the data process of TOF hit information.Chapter Six presents the test and verification of BESIII TOF Trigger System. First, we confirmed the trigger judging logic through on-line simulation verification. Further tests were then carried out together with the FEERearC module (a test module for data fan-out of TOF FEE System), GTL module and the TMSC module (a test module for data receiving of Track Match System). Results have shown that the TOF Trigger System has satisfied every requirement of the project.