The Research Of High-speed Data-transmission Baseband Board And Its Serial Interface

With the rapid development of embedded processing technology and furtherrequirements of people for high-speed real-time information，many challenges forhigh-performance embedded systems have arised.In traditional embedded systems,improving the speed of the processor can dramatically enhance the systemperformance.But studies have shown that the growth of CPU available bandwidthcharacterized by bus frequency is slower than that of CPU core performancecharacterized by clock frequency relatively.And the gap between them is graduallyexpanding. Therefore, improving the speed of the processor has been a very weakinfluence for the improvement of system performance,while the speed ofcommunication between the different modules in the system has become the importantfactors in improving the performance of high speed embedded system.In order to solvethe above problems, and to meet the present and future high-performance embeddedsystems demand at the same time,a efficient and high reliable interconnect agreementdesigned for high-performance embedded system and board-to-board interconnectdesign,using the peer-to-peer operation to realize the effective congestion controlcalled RapidIO has emerged.For meeting the needs of embedded systems as well as the limitations oftraditional interconnect,the RapidIO protocol has made the followingimprovements,improving the efficiency of packaging,reducing the transmission delay,simplifying the flow control mechanisms and protocols, limiting the complexity ofsoftware, making error correction and retransmission mechanism even the entireprotocol stack is easy to implement, supporting multi-rate transmission mode and avariety of physical layer technology,making flexible and easy to extend.This article is based on the high-speed interconnect bottleneck faced byhigh-performance embedded systems and the superiority reflected by RapidIO,havingmade some analysis and research for RapidIO technology as follows, First,brieflydescribing the research background of serial RapidlO agreement, and its developmentat present stage.Secondly, deeply studying the RapidIO protocol structures. In order tomeet the requirements of flexibility and scalability, RapidIO protocol is divided intothree parts: the logical layer, the transport layer and the physical layer, the mostimportant feature of this hierarchy is modifying any layer of the transaction type willnot affect the other layers,and then explaining how to build the high-speed digital transmission baseband.Finally,for the RapidIO agreement, we achieve its high-speedserial interconnect between the FPGA chip and DSP chip by designing the portinitialization, flow control and error management on this hardware platform,describingthe application of RapidIO in present high-speed data-transmission systems andmaking the corresponding simulation. Through the theoretical analysis andexperimental results,we can be seen RapidIO has obvious advantages in performancerelative to other interconnection architecture,and become one of the best choice forembedded systems interconnection.