Research On Sequential Equivalence Checking Based Soft Error Reliability Analysis Of Combinational Logic Element

As the integrated circuits manufactured in more advanced technologies, theimpact of latching-window masking and electrical masking factors is decreasing in logic,making the sequential circuit more susceptible to soft errors. Below 50nm, soft errorcaused by combinational logic element is equal to the soft error caused by sequentiallogic element. The technology of Intel westmere-EP MPU is 32 nm. It means that therealiability of circuit is become more sensitive to the soft error come fromcombinational logic element.Most of the existing approaches for system-level reliability evaluation of circuitscan be classified into two categories: simulation based approaches and formaltechniques based approaches. Though simulation based approaches are used mostwidely, they are incomplete since they cannot cover the input space and fault spacecompletely. Formal techniques based approaches are complete, but most of theconventional approaches based on formal techniques are based on property checkingand theorem proving, which both require experience and support from experts.Moreover, theorem proving needs manual intervention.A fault propagation characteristics and SEC guided Combinational Logic Elementsoft error reliability evaluation approach is proposed. For scalability, fault propagationsequential dependence graph (SDG) is advanced to extract the soft error propagationcharacteristics. In this approach, equivalence checking is localized in the circuit partsaffected by soft error propagation. Experimental results indicate that the proposeapproach not only can locate all the soft error vulnerable spots, but also can check theeffectiveness of the protection logics in circuits.