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Research And Implementation Of Encoder Detection Device Based On SOPC

Posted on:2014-08-25Degree:MasterType:Thesis
Country:ChinaCandidate:Y Y YangFull Text:PDF
GTID:2251330422962876Subject:Mechanical and electrical engineering
Abstract/Summary:PDF Full Text Request
The encoder is the core component of the position measurement device in CNCsystem. Interfaces of the encoders from different manufacturers are different andincompatible. Therefore, these different encoders need to be tested when developing CNCsystem. Currently, encoder detection platforms developed by their manufacturers are lackof versatility. Consequently, it is of important practical significance to develop a testplatform that supports encoders from different manufacturers. Combined with the majorproject of national science and technology, a portable encoder detection device supportingdifferent encoders has been studied. The major contents of this thesis include:Three types of widely used interface of encoder have been deeply analyzed, includingsine-cosine interface, TTL interface and digital serial communication interface. Threetypes of serial communication protocols have been researched, including Endat, BISS andTAMAGAWA. A method of synchronizing the signal of clock and data has been proposedto solve the problem of clock and data signal synchronization existed in the serial digitalcommunication system. The frequency of the transmission clock of the serialcommunication has been effectively improved by this method. The length of thecommunication cable has been extended simultaneously.An encoder detection device with multi-format interfaces has been designed, whichutilizes high-performance parallel processing capabilities of the FPGA and SOPCtechnology based on Nios II processor. The hardware design of the Multi-format encoderinterface has been discussed in details. The hardware platform design of SOPC systembased on FPGA has been discussed. The hardware reliability of encoder detection devicehas been deeply analyzed.IP cores for multi-format Encoder interfaces and Human–Machine Interaction havebeen developed in a FPGA chip, which adopt a modularized design method. These IPcores have been connected to Nios II processor through Avalon bus, which implementsdata interaction among them. The underlying driver programs of these interfaces havebeen developed, which adopt layered software architecture. Hardware devices have been abstracted application interfaces by these programs, which improve the portability of thesystem.The functions and performance of encoder detection device developed in this thesishave been tested detailed. The test results show that encoder detection device developed inthis thesis can meet the requirements of detection of various encoder interfaces and serialcommunication protocols.
Keywords/Search Tags:Encoder, Multi-format, FPGA, SOPC, NiosⅡ Processor
PDF Full Text Request
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