Design Of Universal Signal Processor Based On High-speed Serial Switch

At present, the algorithm of digital signal processing is becoming more and more complex and a great challenge is presented for the signal processor due to large amounts of data and high computational complexity. According to the requirements of large-scale computing, the signal processor is generally integrated into numerous processing nodes to achieve a parallel processing. When increasing to a certain number, the interconnect point-to-point methods will significantly limit the transmission bandwidth of data and then affect the overall performance of the signal processor. Therefore, the study has a realistic significance for the scalable signal processor based on high-speed serial switch because any nodes in the system can share the independent high bandwidth.With FPGA and the multi-core DSP, the thesis describes a design of a universal signal processor based on a high-speed serial switch. Details are shown as follows:(1) The whole designing scheme of signal processor is given. We choose the strong performance of FPGA and DSP as processing nodes on the basis of its development and verification. Meanwhile, we employ the interconnection of each processing node on the latest SRIO and PCIe switch chips.(2) A detailed analysis of the processor chip on power(voltage value, voltage type, and current value) and clock(clock frequency and level logic) needs is given. Then, it draws up the corresponding design scheme of power and clock. After that, this thesis introduces the design principles and thoughts of data switching module, describes the interconnection ways of each interface, and confirms the configuration methods of each processing node and switch chip. Furthermore, the power and signal integrities should be paid attention to when the signal is transmitted at a high-speed mode when the multi-layer laminated structure of the PCB is set up.(3) This thesis emphasizes on the collocating flowchart of registers of every switching chips and the development of FPGA and DSP based on the driver’s side of every high-speed serial protocol and data package format. Also, we compiled test program for data transmission by switching chip at every processing nodes, achieving the purpose of a flexibility of data transmission at these data processing nodes.Even though this thesis achieves a flexible data transmission, there is a gap between the transmission rate and its theoretical value, which should be further improved. Despite that, this proposal adopts the basic functions of the transmitting chip, for which more complex and promising properties are needed to be designed.