Soft Error Mitigation Techniques For Xilinx Virtex-7 FPGA

The SRAM-based FPGA, which has advantages of high performance, high logic density, reconfigurability and other characteristics, is more and more popular in space application, and become the key components of signal processing, data transmission and control system of spacecraft. However, due to the special structure, it is very sensitive to radiation, and the soft error caused by Single Event Upset(SEU) is the main influence. The configuration memory occupies the largest area and is most likely to be affected by the soft error. On the other hand, it can not be protected by traditional ways, so it is very important to study the soft error mitigation strategy of the configuration memory.This paper chooses Xilinx Virtex-7 XC7VX485 T FPGA as the target device and studies the soft error mitigation strategy of the configuration memory. A system level scheme is proposed for soft error mitigation, and this scheme can effectively reduce the influence of soft errors in configuration memory, so as to improve the reliability of FPGA system. According to the scheme, this paper designs a scrubbing system for FPGA configuration memory. The system reads back frame data through ICAP and detects the error by FRAME_ECC circuit. When a ECC error is detected, the system corrects the error according to the syndrome from FRAME_ECC, and writes the right frame data to configuration memory through ICAP. The system has the ability to detect 2 bit errors and correct 1 bit error in one frame.For most applications, the user circuit can not occupy all of the logical resource of FPGA. It means not all of the configuration frames will influence the function of user’s circuit. In this paper, we call the frames associated with the user’s design as the key frames, and assign most of the error detection and correction time to the key frames. In this way, it can effectively reduce the average time of correcting errors, so as to improve the soft error mitigation effect of the system.Finally, the verification results show that the scrubbing system has the ability to inject multi-bit errors to the configuration memory, and the ability to detect 2 bit errors and correct 1 bit error in one frame. Compared to SEM Controller, The average error correction time of the scrubbing system is shorter, which means that the system has a stronger ability of soft error mitigation. Also, the scrubbing system designed by this paper occupies only 0.1% of the FPGA logical resource, which has a very small area and power overhead. Because of the smaller occupied area, the possibility of SEU occurring on the scrubbing system is lower. So the system has a high reliability.