Research On Fault Tolerance Technology Of SRAM FPGA In Radiation Environment

SRAM-based FPGAs are becoming more popular in space-mission applications due to their fast reprogrammability,high logic density,and high performance.However,because of the CMOS process technology,they are easily affected by ionizing radiation particles in the space and other irradiation environments,resulting in single event upset(SEU)which could change the states of memory cells.Configuration RAM(CRAM)has the largest number of memory cells on an FPGA device.Since an FPGA's CRAM stores the implementation of a user design,bit flipping on CRAM has the possibility to cause the design to function improperly.Therefore,the study of SEU fault-tolerant techniques for CRAM is especially important for high-reliability applications of FPGAs.In this paper,we analysis the frame structure of CRAM of Xilinx Virtex-5 series FPGA.The method of processing the frame structure and the order of the frames in the configuration bit stream are given in the article.Through the research on the Xilinx Essential Bits technology,the essential bits,which are related to user design,are extracted from the configuration bit stream file on the basis of analyzing the structure of SEM IP core's intermediate file,thus greatly reducing the amount of data to be processed.A complete SEU mitigation system based on internal ICAP port to access CRAM is designed,and the automated test flow on a PC test interface is also included to facilitate user monitoring and debugging.The SEU mitigation system designed on the XC5VFX70 T device can realize fault injection,the entire frame readback,fault repair and function test of the design under test(DUT).Three DUTs and three benchmark circuits of Microelectronics Center of North Carolina(MCNC)benchmark suit are tested for fault classification,fault injection and fault repair.Fault classification divides the essential bits into critical bits and non-critical bits according to whether they affect the function logic of DUT.The triple modular redundancy of DUTs are also being tested.Fault injection and repair test are designed into three sets of experiments—all critical bits,all non-critical bits,and mixed injection of critical and non-critical bits.The results of experiments are verified and analyzed to give the guidance of engineering application.The designed SEU mitigation system can achieve one-bit error correction and two-bit error detection in a single frame.Under 50 MHz working clock,the error detection time per frame is 2.42?s,and the error correction time is 2.48?s when single bit upset in each frame.Occupied approximately 1% of the FPGA slice resources,the system designed requires no processor,no external hardware overhead,and can be flexibly transplanted to other FPGAs supporting ICAP.