Research On Radiation-hardened Technology On SRAM-based FPGA

Field Programmable Gate Array(FPGA)is widely used in scientific research and commercial fields because of its flexible configurability.SRAM-based FPGA is favored by aerospace field because of its rich resources,strong performance and reconfigurable advantages.However,different from the ground environment,there are a lot of radiation effects in the space environment,including the Total Ionizing Dose(TID)and the Single Event Upset(SEE).SRAM-based FPGA is very sensitive to Single Event Upset(SEU)effect because of its structural characteristics,which greatly limits its application in aerospace field.The antiradiation technology of SRAM-based FPGA has become a hot research topic.Triple Modular Redundancy(TMR)and configuration memory scrubbing are effective methods of FPGA radiation protection,but each has its own shortcomings: TMR structure can't correct errors,and when user circuits are very large,a lot of resources will be consumed;scrub circuit of scrubbing method itself is sensitive to radiation.In this regard,this paper proposes a Real-time Redundant Scrubbing(RRS)system,which combines TMR structure and scrub circuit.Based on the traditional configuration scrubbing,TMR structure is applied to the scrubber.Firstly,a configuration memory scrubbing system on SRAM-based FPGA is designed.The system reads back configuration data by frame through Internal Configuration Access Port(ICAP),and then uses the FRAME?ECC circuit to perform ECC verification.If a 1-bit error is found,modify it according to the verification information,and then write the correct configuration data back to the original location to realize the error correction of the configuration memory.Secondly,the scrub circuit has been hardened with TMR.The traditional TMR structure has been improved,and an error indicator has been added.Whenever the output of any redundant block is different from the other two,the error indicator will give an alarm,so that the system scrubs the scrub circuit immediately,thereby preventing the accumulation of errors and realizing the real-time scrub of the scrub circuit.Thirdly,a distributed floorplan is performed on the scrub circuit.The EDA tool tends to lay the relevant variables in a similar position when the floorplan is automatic.At this time,one SEU may affect multiple redundant blocks,which will invalidate the TMR structure.Therefore,this paper has carried out a distributed floorplan on the scrub circuit,separating the three redundant blocks of TMR.In this way,it is difficult for one SEU to make two redundant logic errors at the same time,which further improves the system's anti-radiation capability.In addition,a fault injection system is designed.The fault injection system is similar to the scrubbing system.Firstly,the configuration data of a frame is read back through the ICAP interface,and then one bit of the frame is flipped and written back to the original position to simulate the SEU.The RRS system designed in this paper can be easily and flexibly tested and verified by fault injection system.After verification,the proposed RRS system can realize 2-bit error detection and 1-bit error correction of FPGA configuration memory.Although the area is about 3 times of that of traditional configuration memory scrubbing system,the total amount of resources occupied is very small,and the anti-radiation capability ability has been significantly improved.