A Study Of Key Techniques Of JESD204B High-speed Serial Interface

The JESD204B standard is JEDEC's recently announced extensible high-speed serial interface standard,which is designed to solve the problem of interconnecting the broadband converters with other system IC devices.The JESD204B standard utilizes the device clock and adds measures to ensure deterministic latency while supporting multiple aligned multi-aligned serial channels.The data transfer rate can be 12.5 Gbps.In this thesis,we use Xilinx FPGA GTH to realize the data transmission interface between the transmitter and the receiver based on the JESD204B standard,and gives a specific circuit implementation.The behavior of the design is realized by verilog,and the transmitter and receiver interface circuits are designed to be compatible with three device subclasses.It has the advantages of few pins,small package size,high efficiency and low cost.The JESD204B interface performs sample conversion and frame assembly by adding control characters and tail characters.Specifically,the data samples for each channel are packed into four 8-bit bytes to implement byte mapping of the converter-to-channel link.Then,based on the polynomial 1+X¹⁴+X¹⁵ to achieve self-synchronization parallel scrambling to reduce the peak spectrum of the EMI effect and data error.Based on the JESD204B standard,this thesis establishes a special data link layer,which improves the transmission of the entire data link layer by initializing frame synchronization,initializing channel synchronization,deterministic delay,frame alignment monitoring and correction.At the same time,it also applies the 8B/10B coding and decoding method for encoding and decoding,and generating a special control character,so as to realise the channel alignment monitoring and maintenance.The JESD204B transmitter and receiver module designed in this thesis contains four channels.The data bit width of a single channel is 32 bits,which is encoded by the 8B/10B unit.The single channel 40 bit data is transferred to 2 differential electrical channels via the high-speed serial transceiver GTH.The FMC interface is connected to the receiver link to simulate the JESD204B physical layer path.The GTH reference clock is configured to 156.25MHz.The simulation results show that the designed interface circuit meets the requirements of JESD204B and achieves stable 6.25Gbps rate a channel.The verification platform is Xilinx Kintex series UltraScale architecture development board KCU105,the maximum support data rate is 16Gbps,and the development tool of the design is Vivado2015.1 integrated development kit.