The DFT About Circuits Of High Speed Serial Interface Based On JESD204B Protocol

As the resolution and sampling rate of data converters increase constantly,the traditional CMOS and LVDS differential parallel interface can not meet the requirement of high-speed interconnection between data converters and logic devices(FPGA,ASIC).Not only surfferring from the frame alignment and intersymbol interference,the low data transfer rate of CMOS parallel interface and LVDS parallel interface also caused by large amount of pins and the complexity of routing.These factors result in the transition of data converter from a parallel interface to a high-speed serial interface.In 2013,Joint Electron Device Engineering Council(JEDEC)publishedthe latest standard of scalable high-speed serial interface,which called JESD204 B.JESD204B interface is a high-speed serial interface,which has functions of channel detection,frame formation,coding,scrambling and multi-chip synchronization.The single channel data transfer rate is up to 12.5Gbps.Due to the complex functions and advanced process implemention,the way to do the performance verification and the reliability testing ofthe designed interface is also very important.JESD204 B protocol is mainly divided into a transport layer,a scrambling layer,a data link layer,and a physical layer by functional hierarchy.The transport layer has the function of group frame,which is responsible for mapping the sampled data according to a certain form.The scrambling layer,makes the data looks like "noise" by randomizing the data after framing which facilitates the subsequent analog processing of the data.The data link layer has code group synchronization,initial channel synchronization,character insertion and replacement,and 8B/10 B encoding etc.The JESD204 B transmitter interface circuit designed in this thesis supports four14-bit 250 MSPS ADC sampling data to be transmitted on two channels and each channel supports a data transfer rate up to 12.5Gbps.The data is transmitted in frames.By 8B/10 B coding,it transfer a frame of 32 data bit width to 40 data bit width in eachchannel.The transmitter circuit mainly comprises a framing module,a scrambling module,a K code and an ILAS code generator,a character insertion and replacement module,and an 8B/10 B encoding module.These modules are designed according to the protocol specification.To test and verify the functions of the framing module,the scrambling module and the 8B/10 B encoding module,a test circuit module is also designed in this thesis.