Design And Implementation Of JESD204B High Speed Serial Interface In ASIC

With the rapid development of communication technology,analog to digital conversion chips(ADC)and digital to analog conversion chips(DAC),as a bridge between the digital world and the analog world,are increasingly in demand.The sampling rate of chips has developed from MS/s to GS/s,and the sampling accuracy has been improved from 6bits and 8bits to over 10bits.The higher sampling frequency and higher resolution require higher transmission speed of the chip,and the common LVDS(low-voltage Differential Signaling)parallel transmission interface can no longer meet the requirements.The reason is that the maximum transmission rate of LVDS interface is 1.25Gbps,which cannot meet the requirements of high-speed data transmission.Moreover,LVDS interface requires a large amount of chip pin and wiring resources,which is easy to produce crosstalk and lead to error code,and is not conducive to the realization of chip miniaturization.In order to meet the demand of high speed data transmission,JEDEC has introduced the JESD204B interface technology,which is dedicated to high speed serial data transmission.The JESD204B high speed serial output interface technology can support up to 12.5 Gbps data transmission per link channel,and support the deterministic delay function,which has been widely concerned in foreign countries.At present,domestic research on JESD204B interface technology is still in the initial stage,and most of it is in the stage of research based on FPGA(Field Programmable Gate Array),and few of it is realized through ASIC(Application Specific Integrated Circuit),namely chip design.In order to meet the transport needs of high speed and high precision ADC chip,this article is based on the analysis of JESD204B the sender interface technology,through the Verilog language behavior level design of the circuit was designed to meet the requirements of JESD204B transport layer and link layer related circuits,including data transmission circuit,synchronous alignment circuit,coding circuit and related control circuit,etc.,applied to the independent research and development of the 3 GS/s-12 bit ADC chip,complete the corresponding digital backend layout design.The ADC chip adopts a total of 8 link paths to realize the design requirements of each link path transmission at a rate of 7.5Gbps,and the flow chip is completed based on the 40nm CMOS process.After the completion of the chip,this thesis designed the corresponding ADC test circuit based on FPGA7K325T platform,tested the function and performance of the ADC,so as to verify the stability and reliability of the circuit JESD204B proposed in this thesis,and designed the deterministic delay verification circuit,and successfully verified the function.The design of the JESD204B output interface circuit proposed in this thesis is very important for the development of high-speed and high-precision digital-to-analog conversion chips,which can effectively increase the transmission rate and reduce the chip power consumption.At the same time,it also played a certain role in promoting the development of the subsequent JESD204C interface technology.