Study And Design Of High Speed Data Transmission Platform Based On JESD204B Standard

With the development of information technology and the improvement of data processing speed,the design scheme of high-speed data transmission platform to support higher speed converters has become a new problem to be solved in the design of new integrated circuits.The high-speed data transmission scheme based on JESD204 B standard has been developing rapidly in the field of high-speed data transmission because of its advantages in speed,flexibility and miniaturization.Traditional data transmission adopts parallel mode such as LVDS and COMS.Because it is vulnerable to intersymbol synchronization and crosstalk,and PCB wiring is complex,it is difficult to meet the design of multi-channel,high-speed and miniaturized data transmission platform.In order to overcome the low speed and poor flexibility limitations,a design scheme of high-speed data transmission is proposed in this thesis.Due to high speed Serdes technology based on data transmission standard JESD204 B,the parallel processing speed of FPGA is reduced,and the flexibility of the system is expanded.In order to verify the effectiveness of the scheme,the Kintex-7 series FPGA chip of Xilinx company is used as the core and TI's high-performance AD/DA is designed to a high speed data transmission platform for TDD technology,which can be configured on the uplink and downlink for G.Fast technology test.The hardware design of the platform includes the design of the control system based on SD5113 and the design of the FPGA module.This thesis will focus on the FPGA logic design of the platform.The FPGA logic design consists of six modules,which are Localbus_Ibus module,Ibus_AXI₂04B_tx/204B_rx module,Ibus_Dataram module,Ibus_SPI_Dac/Adc module,Ibus_Control module and Dataram_Switch module.Considering the flexibility of the system,a configurable switch is set up in the transmission data exit to realize the configuration of the downlink ratio on the TDD signal.Finally,by building a test platform and using a G.Fast signal with a bandwidth of 106 MHz,the effectiveness of the high speed data transmission platform is validated.In the data receiving and receiving test,the multitone power ratio?MTPR?calculation needs to extract useful signals from the whole receiving signal due to the discontinuous time domain and downlink time division multiplexing?TDD?signal in time domain.In this paper,the cross correlation function is innovatively used to find the boundary of the Symbol and the MTPR of the TDD signal.The test results show that the design realizes the configurability of the downlink ratio on the TDD signal.At the same time,the error of the TDD signal of the sending end is less than 1.366%.The MTPR of the whole transceiver system is above 50 dB,which meets the requirements of the G.Fast technology test.