Soft Error Protection Of Digital Integrated Circuits

With the progress of semiconductor technology,the integration degree of integrated circuits increases,the size decreases,the supply voltage decreases,the power consumption decreases,and the processing speed of integrated circuits increases.Great progress has been made while increasing the sensitivity of the chip to soft errors caused by radiation.Soft errors are usually caused by transient faults,which can be divided into single Event Upset(SEU),single Event Transient(SET)and so on.Soft error tests on one of Intel's chips show that 89% of the chips are SEU and 11% are SET.For integrated circuits,reliability issues need more and more attention.This paper studies the soft error protection of digital integrated circuits,and proposes two anti-SEU latches.In this paper,we first introduce the history of integrated circuits,the introduction of soft errors and HSPICE simulation tools.Secondly,we introduce some classical SEU protection latches.When high-energy particles bombard sequential logic circuits(such as latches,flip-flops,etc.),the logic values of sequential logic circuits are reversed,which is called single event inversion(SEU).1.This paper presents an improved SEU tolerant latch based on error detection,which consists of an improved standard static latch and an error detection circuit.It solves the problem that the original error detection circuit of the latch can not protect SEU.The improved standard static latch can be detected by the error detection circuit,thus controlling the selection of the improved standard static latch.The correct path is chosen for output,while the SEU in the error detection circuit is corrected by the feedback loop composed of C units.Compared with the three modular redundancy(TMR)latch,the proposed latch power consumption is reduced by 77.5% and the transmission delay is reduced by 33.1%.2.Aiming at the fault-tolerant problem of high-frequency circuit,a SEU tolerant latch with low transmission delay applied to high-frequency circuit is proposed.It is a simple symmetrical structure,which can effectively reduce the area overhead and transmission delay.Through the C unit itself,SEU can be prevented from occurring at the nodes on the feedback circuit,and SEU can be prevented from occurring at the output of the C unit through the symmetrical structure of the upper and lower parts.Compared with the three mode redundancy(TMR)latch,the latch transmission delay is reduced by 69.86% and the area overhead is reduced by 38.89%.Compared with the RHBD latch,the transmission delay is reduced by 69.92% and the power consumption is reduced by 98.24% compared with the HPST latch.Compared with the HPST latch,the transmission delay is reduced by 70.84% and the area overhead is reduced by 21.43%.The two latches proposed in this paper can effectively protect SEU and improve the reliability of digital integrated circuits.Compared with the existing SEU protection latches,they also have certain advantages in power consumption,transmission delay and area overhead.Figure 36 table 10 reference 52...