Design And Implementation Of Serial Data Interface Based On JESD204B Protocol

With the development of modern communication,military and spaceflight,applications of high-speed and high-precision converters emerge one after another.The traditional data transmission interface circuit,such as CMOS,LVDS,cannot meet the demands of converter's development.Therefore,the design of a high-speed data transmission interface circuit has become a hot topic in the application of high-speed converter.This paper establishes a high-speed serial data transmission port based on JESD204B.It can transmit high-speed serial data between 12-bit,1.6 GSPS,quad analog-to-digital converter and logic devices?FPGA or ASIC?.According to the hierarchical structure of JESD204B protocol,this paper studies the related functions of each layer in data transmission,and designs the corresponding modules to realize these functions.The data transmission interface firstly packages the multi-bit sample data sampled by the converter into a series of non-scrambling 8-byte formats according to the relevant rules generated by the link parameters,in the transport layer.Then the data that need to be scrambled is fed into the scrambler,which uses a self-synchronizing,polynomial-based algorithm defined by the equation 1+X¹⁴+X¹⁵.Scrambling is optional,however,it is recommended to avoid spectral peaks when transmitting similar digital data patterns.According to JESD204B protocol,a special data transmission link is established at the data link layer through code group synchronization,initial lane alignment sequence and character replacement,and the method of deterministic latency and frame clock alignment is used to improve the accuracy of data transmission.At the same time,the 8B/10B encoding method is used to encode the data so as to keep the DC balance of the transmission link.The corresponding special control character is also generated to realize the function of error monitoring and maintenance of the lane.Finally,the physical layer adopts SerDes structure,which mainly realizes the serial-parallel conversion in data transmission,and can simulate the physical layer of JESD204B protocol through GTX high-speed serial transceiver.This paper applies the Verilog hardware description language to design the circuit based on the FPGA development software Vivado,of Xilinx Company,and carries out circuit simulation verification in Vivado platform.By analyzing the simulation results of each circuit module,it is proved that the interface can achieve the highest data transmission rate of 12Gbps.Compared with the traditional interface,this kind of high-speed serial interface based on JESD204B standard has lower power consumption,smaller IC package,and meets the needs of the industry for higher bandwidth of converters,and has gradually become the mainstream data transmission interface of gigabit converters.