High Performance Digital Controller For High-frequency Low-power Integrated DC/DC SMPS

Most of phones, PDAs and music/video players are still mainly designed with analog PWM control inside the voltage regulator blocks. Despite being a popular research topic, digital control is still seldom applied in low-power high-frequency integrated Switching Mode Power Supply (SMPS) converters. This is mainly due to the complexity of implementation, cost constraint and absence of digital controller architectures that can support operation at switching frequencies significantly higher than 1MHz with low-power consumption features. Broader acceptance of digital techniques in low-power high-frequency SMPS is still hampered by practical problems of the combination of cost issues, trade-off performances and power consumption.However, compared to analog control, digital control technique has much more remarkable advantages. The research interest of the thesis is to explore practical ways of incorporating advantages of digital control in SMPS implementation, investigates issues of digital controller implementation at lower power levels, gives detailed guidelines for digital controller design and hardware selection, and proposes new hardware solutions for the main functional digital controller blocks. Two main objectives of this work focus the implementation of high-resolution high-frequency digital PWM (DPWM) and high-performance digital control algorithms for SMPS in FPGA-based realization.To aim at the contradiction between the high-frequency DPWM and high-power consumption of digital controller, we proposed two kinds of new Hybrid DPWM architectures:Hybrid dither DPWM and Hybrid Delta-Sigma DPWM, which are addressed to increase resolution and reduce power consumption simultaneously. The efficient high-frequency high-resolution DPWM architectures can not only improve the output voltage accuracy of SMPS, but also can eliminate limit cycles phenomenon. The proposed DPWMs featuring high-frequency, high-performance, high-resolution, low power and small size, can solve the issue between the high-resolution and high-power consumption, and improve the DPWM effective resolution while reducing the system high-frequency clock simultaneously.In order to improve the dynamic performance of digital controller and reduce the energy consumption of algorithm computation simultaneously, a Tri-mode controller consisting of a PID and robust RST controllers is proposed. The Tri-mode digital controller addresses transient, steady-state and stand-by modes. To accommodate fast dynamic response, the RST robust control-law is adopted in transient mode. In steady-state mode, the PID control law is applied to minimize power consumption. While in stand-by mode if the converter is light-loaded, then the controller is clocked at a frequency lower than the converter switching frequency for consideration of energy consumption.Considering the SMPS is a typical variable structure system (Variable Structure Systems:VSS), a nonlinear Sliding-Mode Controller (SMC) is developed to realize the control of high-frequency low-power SMPS. Due to the inherent shortcoming of variable switching frequency existing in the traditional Hysteresis Modulator sliding mode control (HM-based SMC), we propose a DPWM-based SMC to replace the traditional HM-based SMC in the practical application. The DPWM-based SMC can not only provide high-performance dynamic response, but also feature simple structure, small size and easy integration, etc.Finally we adopted a FPGA to implement the proposed new digital control scheme on a 750 mW high-frequency Buck converter for an instance. Experimental results have proven that not only the efficient digital control at low power levels is very possible, but also the digital control can achieve significant improvements of dynamic performance. An ASIC implementation of the digital controller on 0.35μm CMOS technology is under process.