Research On Network-on-Chip Technology For The Visual Information Processing System

As a promising alternative of the traditional bus and point-to-point connection, Network-on-Chip(NoC) can provide the high bandwidth, low power, high reliability and high scalability communication architecture for SoC. This architecture greatly helps overcoming the design problems and performances limitations of current bus-based SoC methodologies. The characteristics of the NoC architecture make it can be widely used in the field of the visual information processing with its real-time and high-speed data processing and flexible techniques, such as in space remote sensing, aerial photography and security monitoring. The parallel exploration of task mapping and mesh topology is one key technique of the NoC design to achieve one visual information processing system based on NoC with good performance and low energy consumption.The development of the NoC technology are introduced, and its application and significance in the visual information processing field are stated. In order to meet the application requirements of the visual information processing, this thesis focuses on the NoC task decomposition and mapping technique. A novel task mapping algorithm – Branch and Bound based on Latency-constraint algorithm are proposed to speed up the generation of the task mapping scenario with good performance and low energy consumption. To improve the parallel exploration of NoC application design, an exploration flow of task decomposing and mapping on different shapes of mesh NoC with different task mapping techniques are presented. Taking advantage of the FPGA-based NoC emulation platform, the parallel exploration solution are emulated and analyzed. The experiments demonstrate that this exploration flow can help the designer to explore the space mapping of the NoC. These researches devote to the improvement of transmission performance and energy consumption of the visual information processing system based on NoC and provide the theoretical basis for the space mapping exploration of reconfigurable processor and the exploration of the visual information processing system based on No C in the future.The creative work of the paper includes:1. A novel performance and power aware task mapping algorithm based on mesh NoC which combines the latency constraint and branch and bound concepts. With the proposal of latency constraint definition and the selection rule of root node, this algorithm can achieve the better timing performance and lower energy consumption only with nearly half of CPU time of the traditional branch and bound mapping algorithm.2. One exploration flow of task decomposing and mapping on different shapes of mesh NoC with different task mapping techniques is presented. The flow is to evaluate timing and energy consumption of the task mapping scenarios based on FPGA-based NoC emulation platform. The experiments show that the exploration flow can help the designer to explore the appropriate task mapping strategy for the specific application to meet the design requirements.3. A new auto-focusing method which is specific to auto-focusing of multiple sensors put on one line in the system is proposed. In the premise of ensuring the image sharpness, the method can build the multi-objective function between the image sharpness and the focal length value for the multi-sensor system and find the common focal length value with the ideal point method in optimization methodology. By setting the common focal length to multiple sensors, the source images from the sensors have the same depth of the field and the same angle of view.