Study Of On-chip Antenna And Rf/wireless Interconnect

The application of VLSI and ULSI pushes the development of IC, the progress of which has been predicted by the Moore's law. However, the scaling down characteristic size, increasing operating frequency, and scaling up metal interconnects area of IC lead to the development limitation of traditional metal interconnects. For instance, the RC delay, IR voltage drop, CV2 fpower loss and crosstalk of metal interconnect will be the bottleneck of IC development. So, the research and design of new interconnect technology solving the limitation problem of interconnects is increasingly necessary.Antennas have been an indispensable and important part of the wireless communication system. In recent years, some research moves the traditional antennas to the field of chip interconnects. The methods of researching and analyzing wireless communication system are adopted, using on-chip antennas and wireless communication ways instead of traditional metal interconnects. By this way, interconnecting between two function modules or two chips could be realized, and some limitation problems of traditional metal interconnects could be solved to a certain extent. This kind of interconnect is called wireless interconnect. Meanwhile, some research focuses on adopting a few or only one traditional microwave transmission lines (MTL (Microwave Transmission Line) or CPW (Coplanar Waveguide)) as the transmission medium, using kinds of modulation and demodulation modes of wireless communication, uploading and downloading signals via coupling capacitors. By this way, the area of traditional metal interconnects could be decreased greatly, and some limitation problems of traditional metal lines partly solved. This kind of interconnect is called RF interconnect.Based on prevenient research, this paper proposes a signal channel model and noise model of RF interconnect, analyzes its signal transmission and noise characteristics, equalizes the band-signal noise ratio well by using all kinds of modulation modes synthetically. Meanwhile, aiming at the miniaturation, higher gain, low loss, and good directional property of on-chip antennas, several kinds of on-chip antennas applicable in wireless interconnect system are designed. Then, EBG (Electromagnetic Bandgap) and HIS (High Impedance Surface)technologies are used in the design of on-chip antennas and a set of inter-chip wireless interconnect transceiver with on-chip antennas are designed and fabricated. The performance of on-chip antenna and the feasibility of wireless interconnect system are validated. The thesis mainly consists of following research work:1. A channel and noise model of RF interconnect system is constructed and analyzed. The model includes the signal transmission performance of channel, noise characteristics including reflecting noise at ports, switching coupling noise and receiver noise etc. Based on the SNR (Signal Noise Ratio) performance, in order to realize a good balance between bandwidth and SNR, CDMA (Code Division Multiple Access) and MPSK (Multiple Phase Shift Keying) modulation modes are used in this model synthetically and then the performance of whole system is improved.2. In order to improve the performance of wireless interconnect system, a series of miniaturized, higher gain, lower loss, higher directional on-chip antennas are designed and realized. We adopt standard 0.18um CMOS technology to design and fabricate on-chip slot antenna, which proves that it is feasible to design and realize these on-chip antennas under the restriction of standard CMOS rules. The low resistivity silicon substrate ( 10Ω?cm) is used to design on-chip slot antennas. The simulation results show that on-chip slot antennas have higher intra-chip transmission gain than normal on-chip dipole under the same condition. Meanwhile, the same CMOS technology is used to design and realize on-chip folded antennas, which minimize the area of antennas while improve the gain of antennas. Two pair on-chip hackle directional antennas are designed and simulated. Compared with the two pair of antennas, good directional characteristics are obtained and thus the back-end radiation is decreased, reducing the bad impact to the circuits.3. In order to improve the transmission gain and reduce the impact of standard CMOS low resistivity silicon substrate of on-chip antennas, HIS structure is used in our designs. As the application of artificial magnetic conductor (AMC) of HIS structure, the mirror current direction of on-chip dipole is the same as the dipole's and reduce the substrate loss. At the same time, the application of loaded MIM (Metal Insulator Metal) capacitor on HIS decreases the area of HIS farther and saves the chip area. Meanwhile, EBG structure is also applied in our design to tune the input impedance of on-chip antenna, which greatly decreases the on-chip dipole size and restrains the high-order harmonics.4. By TSMC 0.18um technology, an inter-chip wireless interconnect transceiver operating on single frequency is designed and realized. This system operates on 20GHz. The transmitter includes VCO (voltage control oscillator), class E power amplifier (PA) and on-chip dipole with loaded MIM capacitor HIS. The receiver includes on-chip dipole with loaded MIM capacitor HIS and LNA (low noise amplifier) with output buffer. Measured results show that this system works well and prove the good performance of on-chip dipole with loaded MIM capacitor HIS.