| As modern CMOS integrated circuit (IC) technology moves into the very deep submicrometer (VDSM) regime, millions of transistors operating at frequencies greater than a gigahertz will be integrated onto a single IC. Serious on-chip electrical problems, including signal distortion along coupled interconnect lines and voltage fluctuations in the power distribution network, are being encountered in these high speed, VDSM high complexity integrated circuits. This on-chip interconnect noise increases the design cost as well as the design time. Moreover, the noise also causes circuit malfunctions and long term reliability issues. On-chip interconnect noise has therefore become one of the primary threats to continued growth in integration density and circuit performance. In order to ameliorate these design challenges in VDSM integrated circuits, design for signal integrity (DSI) strategies need to be incorporated into existing design methodologies and related design automation tools.; The first comprehensive research on on-chip interconnect noise in CMOS integrated circuits is presented in this dissertation. The primary objective of the research is to develop a capability for enhancing signal integrity in high performance CMOS integrated circuits. This objective has been satisfied by considering design issues in terms of the interconnect impedance models, coupled on-chip interconnect and voltage fluctuations in power distribution networks, permitting the effects of the interconnect impedances, coupling noise, and delay uncertainty to be predicted at the system level in order to improve overall circuit performance. The accuracy of the developed propagation delay model is within 7% for a resistive load and 11% for an inductive load as compared to SPICE. The error of the estimated peak coupling noise voltage is within 7% and 13% of SPICE for a two-line and three-line coupled system, respectively. The predicted peak transient IR voltage drops and on-chip simultaneous switching noise voltage are within 6% and 10%, respectively, as compared to SPICE. The research presented in this dissertation has provided a capability for estimating on-chip interconnect noise at the system (or IC) level, permitting interconnect-based design strategies and related design methodologies to be developed. |
