Research And Design On The Receiver Circuit Of On-chip High Speed Low Power Interconnects

As the digital integrated circuit technology steps into sub-micron andnanometer region, the SOC and NOC have grown up, interconnects tend tobecome the bottleneck of performance and power on large scale chips.Low-swing interconnect, which emerged as the solution to high data-rateas well as low power, has attracted attention in the interconnect area.The aim of the thesis is to design the receiver circuit of low-swinginterconnect, including voltage-mode and current-mode transceivers. Thevoltage-mode receiver consists of improved sense amplifier and decisionfeedback equalization module. The half-rate clock strategy is used todouble the bit-rate, namely2Gb/s through a10mm wire. The averagepower consumption is0.309mW while the energy per unit is0.170pJ/bit.By changing the structure, the voltage-mode interconnect conveys into thecurrent-mode circuit, but its performance and power are equivalent to thevoltage-mode circuit. In the thesis, a new current-mode interconnect isproposed based on the reference paper, involving transmitter and receiver.The bit-rate is2Gb/s, the average power consumption is0.1719mW whilethe energy per bit is0.11pJ/bit, through a10mm wire.According to the results from simulation, the low-swing interconnectgains much advantage in performance and power, comparing with bufferinserting method while consumes lower power comparing with the circuitsin the reference paper.