Research And Implementation Of Addressable Test Chip For SRAM Mismatch

With continuous down-scaling of the integrated circuit, the process of integrated circuit becomes more complex, yield problems caused by defect become more serious. Mismatch of transistors which seriously influences the performance of integrated circuit is also increasing. Worse still is that the impact of mismatch on the transistors in SRAM cells is more obvious, due to the fact that the gate length and width of these transistors is often smaller than the minimum design rule in a technology, the layout of SRAM is denser and the environment of transistors in SRAM cells is more complicated. Test chip is very important in improving yield of integrated circuit, because it can be used to monitor defects, establish product reliability and extract parameter. Addressable test chip become a hot research area because it can meet the requirement of a lot more test structures. We have focused on the research of the design methodology of high-accuracy and high-density addressable test chip for SRAM mismatch:1) Proposed a test structure design methodology for the research of SRAM mismatch. There are3pairs of transistors in SRAM cell, so we have designed3test structure to measure the mismatch of them respectively. These test structures are got from the modification of the original SRAM cell. The principal of layout modification is that the front-end-of-line (FEOL) design remains the same as original SRAM cell, and part of metal line are modified to isolate DUT. The layout of modified test structure is still symmetric.2) Designed addressable test chip for SRAM mismatch which is placed in scribe line. The total area of the addressable test chip is about68*2381um2, and the total number of DUT placed in the test chip is120pairs. The performance parameters such as Idsat, IOff, Vtsat and Vain of every DUT placed in the test chip can be accurate measured. The addressable test chip for SRAM mismatch has been implemented in28nm CMOS technology and measured. The reliability and accuracy of our design has been verified.