Research On Yield Test Chip Design Method For Nanometer Integrated Circuits

As integrated circuits step into nanometer technology era, the complexity of the manufacturing process is becoming higher and higher, new materials and new devices are constantly introduced, the effect of the process variation is becoming more significant. These new issues bring new challenges to yield prediction and test structure design under nanometer era.As an important tool used in the research of yield, test structures are used in multiple stages of product development. They can be used to extract various circuit parameters, detect defects and faults, define and optimize layout rules, evaluate process equipment. Test structures play an important role in shortening technology development cycle, improving product yield, decreasing product cost. On the basis of previous research results of yield and test structures, following work related to test structures are investigated:(1). Via chain design method considering confidence level and estimation precision is proposed. In order to improve the confidence level and estimation precision of parameters extraction, minimize statistical randomness of parameters extracted using via chain test structures, this dissertation proposes the way of determining the range of total number of vias and the number of each via chain through the Law of Large Numbers and the de Moivre-Laplace theorem. When optimizing for area, this dissertation proposes the method to obtain the optimal combination of the total number of vias and the number of each via chain. The results of Monte Carlo simulation and wafer experiments reveal that the proposed method has a better performance.(2). Serpentine structure design method considering confidence level and estimation precision is proposed. This dissertation proposes the way of determining the reasonable total area of serpentine structures and the area of each serpentine structure through the Law of Large Numbers and the Lindeberg-Levy theorem. This dissertation investigates the method to obtain the optimal combination of the total area of serpentine structures and the area of each serpentine structure when area optimization is aimed. Given specific confidence level and estimation precision, the proposed design method improves the precision and economic efficiency when extracting average defect density for interconnecting layers,(3). Using pseudo transistor arrays for extracting defect density of gate oxide shorts is proposed. Pseudo transistor arrays which have the same structure and manufacturing process are proposed in this dissertation to extract defect density of gate oxide shorts. The pseudo transistors can imitate the formation of defects on normal transistors and the defects can be identified more easily. The results of experiments reveal that, when the defect density of gate oxide shorts extracted using this proposed structures is used to predict yield of products with the same fabrication process, the predicted data matches well with the measured data in electrical test.