Architecture And Microarchitecture Design Research Of RISC/DSP Processor

Rapid development of integrate chip technics has driven the system into System-On-Chip (SOC) age. Novel processor architecture is widely studied to fulfill the rapidly growing demand of embedded system. Traditional Reduced Instruction Set Computer (RISC) and Digital Signal Processor (DSP) have different application areas due to their different Instruction Set Architecture (ISA) and micro-architecture. RISC/DSP is a hybrid of traditional RISC and DSP processor, and is more capable in embedded application area with both characteristics of RISC and DSP.The author of this paper attended the project of RISC/DSP processor design-MD32,which is development by the Department of Information Science and Electronic Engineering in Zhejiang University, and studied the design methods of ISA and microarchitecture. MD32 ISA is a novel architecture, which features with both RISC and DSP. Single Instruction Multi Data (SIMD) is also supported in MD32. A characterized RISC/DSP micro-architecture and unified pipeline is designed based on MD32 ISA. It is not only good at executing system tasks like RISC processor, but also expert in digital signal processing like DSP. This makes MD32 more powerful in multi-media signal processing. The main contents and innovative points in this paper include:Define an instruction component and partition model. Conception of orthogonal instruction set is presented based on the instruction component formula. Relations between instruction orthogonality, architecture complexity and data path design are studied. ISA is divided into three parts according to the design consideration of MD32. Rich addressing and operation modes are supported in MD32 ISA.RISC/DSP pipeline partition rules are given based on the relations between instruction set and data path design. After analyzing and comparing different partition rules, MD32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of MD32.A complete set of creative design method for RISC/DSP MD32 micro-architecture is presented, such as parallel design, internal pipeline, central control, etc. Thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages.MD32 verification platform is also studied in this paper. MD32 verification is implemented in both FPGA hardware verification platform and software verification platform, which achieve unit, architecture and system verifications. MD32 processor can be sufficiently verified on these platforms.