Research And Design Of Pipeline Based On Embedded RISC-V Microprocessor

With the continuous development of artificial intelligence,embedded electronic products have been widely used in people's life,and the performance of embedded microprocessor has been paid more and more attention.The embedded microprocessor based on traditional instruction set architecture cannot meet requirements of the extensive application in the embedded field.Especially in terminal equipment of the embedded IoT,while the low power consumption of the processor is met,the requirements for data calculation and processing of the processor are also more and more highly raised.And it is difficult for an embedded microprocessor with a pipeline structure of sequential launch,sequential execution,and sequential write-back of the traditional instruction set architecture that the power consumption and performance are took into account at the same time.The new RISC-V architecture has the advantages of simplicity,modularity,and customizable extensions.For the low-power and high-performance requirements in the embedded field,it is of great significance to design a processor pipeline structure with sequential launch,out-of-order execution,and chaotic of sequential write-back based on the RISC-V instruction set architecture.In this paper,the RISC-V architecture was analyzed,and the RV32IM instruction set in the RISC-V instruction set architecture was implemented.Requirements of the pipeline structure and functional,the conflicts on the pipeline and the RV32IM instruction encoding characteristics were also analyzed.Then a three-stage pipeline structure of sequential launch,out-of-order execution,and out-of-order write back based on RISC-V-based instruction set was proposed.The branch prediction module and OITF module were designed to solve the control conflict and data conflict in the pipeline.And the pipeline design of the embedded RISC-V micro-processor was designed.The processor pipeline includes the instruction fetching,decoding,and execution units.The RTL design of the top-level fetch unit is composed of four modules of PC generation,ICB bus control,Mini-Decode,and branch prediction.The RTL design of the top-level decoding unit is composed of four modules of integer general register group,instruction decoding,instruction launch,and OITF.The RTL design of the top-level execution unit is composed of four modules of arithmetic and logic operation,storage access,write-back,and delivery.The fifty-on kinds of instructions in the RV32IM instruction set are divided into single-cycle execution instructions and multi-cycle execution instructions according to the operating clock cycle.Three kinds of the load/store instructions and multiplication and division instructions in the single-cycle execution instructions and multi-cycle execution instructions were designed to be executed in parallel.Regula-ALU,AGU and MDV of the independent arithmetic units effectively improve the execution efficiency of instructions.The multi-period multiplication,divider and the three arithmetic units adopted by the multiplication and division operation unit are equipped with independent clock gating,which further ensures the low power consumption for the design of the overall structure of the three-stage pipeline.The hardware implementation of the three-stage pipeline structure of sequential launch,out-of-order execution,and out-of-order write-back was completed in Verilog language.The official self-test case provided by RISC-V was compiled by the gcc tool chain.The TestBench for the simulation test platform was built.The simulation of the functional logic correctness of the pipeline of the RISC-V microprocessor was done by the VCS tool.The correctness of the fifty-one kinds of instructions in the RV32IM instruction set was verified with the executable binary file generated by the compilation.The CoreMark test program was used to test the performance of the processor pipeline.The program running speed of the processor pipeline is 2.4 CoreMark/MHz.The logic synthesis of the processor pipeline was completed by the DC tool under the typical conditions based on the 90nm process.The IC layout of the processor pipeline was designed by the ICC tool.And the GDSII file was generated.The area overhead is 20.5K logic gates and the power consumption is 0.2 1mW.