Research And Design Of Superscalar Microprocessor Based On RISC-V Instruction Architecture

With the rapid development of the Io T,its most important technical component—Embedded systems have higher and higher performance requirements.As the core of Embedded systems,microprocessors have always been the focus of people's research.Its low-cost and low-power requirements make designers need to consider their design and implementation from all aspects,and ISA and micro-architecture are the most obvious two aspects that affect the performance of a microprocessor.As traditional scalar processors are unable to handle certain specific and efficient application scenarios,and the open-source ISA RISC-V has gradually become the object of industry embrace with its excellent features,combined with the RISC-V ISA and superscalar technology,developed a microprocessors for embedded applications have important value and significance.This thesis analyzes the advantages of the RISC-V ISA compared to other RISC ISA for processor design,and designs a superscalar microprocessor based on the RISC-V ISA.At the same time,for the popular information security and data encryption applications in the embedded field,combined with the flexibility of software programming and the high efficiency of hardware acceleration,according to the instruction extension function of RISCV,special extended instructions are designed for the AES encryption algorithm to reduce the number of AES encryption algorithm assembles instructions to improve the speed of the encryption process.On the basis of the designed microprocessor,a corresponding encryption operation execution unit is added to cooperate with the expanded encryption algorithm instructions.The microprocessor adopts a six-stage pipeline depth,a 2-way out-of-order execution superscalar structure,supports the RV32 IM instruction set,and has a Gshare branch predictor to reduce the waste of pipeline cycles caused by branch instructions;Realizes the register renaming function to solve the two instruction dependencies of WAW and WAR during out-of-order execution;For branch instructions and memory access instructions,the instruction failure caused by out-of-order emission is more expensive,so the processor sequentially issues branch instructions and memory access instructions,and issues logic operation instructions and multiplication instructions out of order.The microprocessor uses Verilog HDL language to design and implement,and build a RISCV compilation environment,write assembly instructions to perform functional tests on the processor.The test results show that the microprocessor functions normally,the IPC is 1.12,and the branch prediction error rate is below 0.1,it can meet the needs of embedded systems for microprocessors,and complete AES single-block encryption using 307 instruction cycles,which effectively improves the execution efficiency of the AES encryption algorithm,and is suitable for information security and data encryption applications.