Low Power MP3 Decoder And Its Design-for-Testability Techniques

In this research work, a low power MP3 decoder based on ASIC is discussed. Power consumption is optimized from algorithm level, architecture level and circuit level synthetically. At algorithm level, address generation is proposed to replace conventional bit reservoir buffer; combining look-up table methods and polynomial fits method, a new requantization algorithm, which has higher SNR, faster computation and fewer storage memory usage, is proposed; exploiting the characteristic of MP3 frequency line, algorithms for requantization, stereo processing, anti-aliasing and IMDCT are improved to reduce the computation load. At architecture level, the MP3 decoder takes the advantages of the parallel structure for left channel and right channel, the pipelined structure for IMDCT and Matrixing process, and the pipelined structure for Huffman decoding, requantization and stereo process. The computation time with the parallel and pipelined architecture proposed is only 1/5 of that with the corresponding serial architecture. Meanwhile, a multiplier, which uses both the positive and negative clock edges, is implemented. This double-edge triggered multiplier can reduce multiplying time to 60%. At circuit level, latch and SA-DFF have been used to replace flip-flop in some modules to reduce the power consumption. The adoption of SA-DFF can reduce 13% power consumption at an expense of only 2% area increase. For DFT, a new test method is proposed to test latch blocks. This test method has very high fault coverage and is suitable for latch BIST implementation. Some DFT issues, such as the shadow logic around RAM and latch blocks, the negative clock edge flip-flops and multi-clock scan test, are carefully optimized to yield higher fault coverage and fewer test patterns.The interface of the MP3 decoder is designed for reusability. It can adapt to different On-Chip-Bus systems, with multi-clock domain applications and with variable interface-timing requirement. The MP3 decoder designed is superior in low power consumption as compared with software implementations based on DSP or RISC CPU and other ASIC MP3 decoders.