The Physical Implement And Synthesis Of H.264 Video Decoder Based On GF14nm Technology

In recent decades, with the continuous improvement of technology, the complexity of ASIC is also increasing, the manufacture of smaller size and larger chips is becoming more and more difficult. Based on the global foundry 14 nm process This paper implements soft core of open source code to be the hardcore decoder with better performance, lower power consumption, stronger reuse.Firstly, this paper introduces the principle and key technology of H.264, and completes the optimization of the test code and the function simulation of the front end. In the synthesis stage, through the clock gating and multi threshold voltage method, the gate level network table of the back-end design is obtained in the GF14 nm process library and related design constraints files. In back-end implementation, this design uses ICC as main tool to realize physical design such as layout planning, power planning, standard cell layout, multi-point clock tree synthesis and wiring etc. This paper introduces the technology of multi-point clock tree synthesis and how to reduce the routing congestion. The stages of back-end design use balance design method, through the iterated timing analysis and optimization means to achieve timing closure, combined with the clock tree synthesis principle of advanced technology and power consumption optimization methods to achieve low power design. Finally, the design passes the physical verification and special timing check, summarizes the causes of common design rule violation and the solutions, discusses the correction method and the principle of ECO(engineering change order) stage.Through the physical design, the working frequency is 200~1000MHz, the area is 278.66×456.19μm2, the working voltage is 0.2~1.029 V and the working temperature is 0~110?C, the power consumption is about 4.57 mW. IP core length is 2.79×105nm, the width is 4.56×105nm, the total area is about 0.127mm2. The total area of standard cell is 7.43×104μm2. Compared with the previous IP core area under the TSMC28 nm process, the area of the designed IP core is only 1.12%. The working frequency and the working range of the design are improved, and the manufacturing cost is reduced.