Hard Core Modeling And The Key Techniques Of Physical Design In VDSM SOC

IC industry has entered the nanometer-scale SOC era. New process technology brings new challenges to the design methodology with feature size scaling down. At the same time, the expansion of the design scale brings new problems in the area of functional design, verification, formal verification and testing. In the area of physical implementation, many new issues such as timing closure emerged due to the scaling down of feature size.The flow of physical implementation and verification is presented in this paper. An advanced IP-based SOC physical design and verification flow for 0.13um process is introduced. The flow solves some critical problems such as timing closure, power, design for testability as well as the reusability of IP cores,Main contributions in this thesis are:1. The physical implementation flow of IP-based design in VDSM is introduced. The key techniques of this flow are analyzed.2. The method of low-power implementation is analyzed. The flow which incorporates various techniques such as gated clock, multiple voltage domain is introduced.3. The flow to achieve timing closure and timing verification considering signal integrity, IR-drop and On-Chip-Variation is introduced. The flow was applied to 0.13um process and achieved a successful tape-out in a quick turn-around.4. The whole suite of techniques to modeling an embedded CPU hard IP core is introduced. It has been applied to an 32-bit high performance embedded CPU CK520. The model generated by this technique describes the IP hard core characteristics accurately, comply to the standard input format in IC industry and easy to use. The IP core peoperty is well protected since the models are provide as a encrypted format or the interface format. There have been several SOC chips which incorporates the embedded CPU IP taped out successfully based on these models. This confirmed the accuracy and usability of the models.5. A novel method for IP timing model extraction of VDSM based on dynamic IP-drop is introduced in this paper. Based-on dynamic IR drop analysis, this method considers the dynamic IR drop in traditional timing model extraction flow so as to calculate the worst-case dynamic IR drop and generate more accurate timing model. Accurate model is one of the key factors which determine the SOC system design quality.New physical implementation flow of processes below 65nm is planned to be researched. At the same time, the models need to be further improved to accelerate the design process of SOC design.