Physical Design Of CPU Core With Several Millions Gates Under65Nanometer Process

IC industry has entered the nanometer-scale age now, the progress of process technology brings many new challenges, such as interconnect coupling by size shrink,timing degrade due to crosstalk and the timing complicated due to a variety of scenario and mode.So whether the layout designer can realize physical design, use EDA tools effectively and improve method or flow according to the design is a key to the success of chip.This paper introduces the back-end physical design process of a CPU core in65nm process based on the tools of Synopsys.The flow is split into several key steps such as partition, floorplan, placement, clock tree synthesis, routing,timing closure. This paper analyze the critical problem and gives out some solution. Considering the interconnect coupling effect of the nanometer process, the paper describes how to prevent crosstalk and fix it. The last chapter introduces the distributed multi-scenario analysis which can make timing clean quickly.The example of this paper is a high performance CPU core that meets the requirement. The SOC chip with the core has been taped out successfully and it works well.